IMX51 Datasheet, PDF (93/184 Pages) Freescale Semiconductor, Inc – i.MX51 Applications Processors for Consumer and Industrial Products

Electrical Characteristics
3.7.8.7.2 Asynchronous Parallel Interface Timing Parameters
Figure 60 depicts timing of asynchronous parallel interfaces based on the system 80 and system 68k
interfaces. Table 71 shows timing characteristics at display access level. All timing diagrams are based
on active low control signals (signals polarity is controlled via the DI_DISP_SIG_POL Register).
IP35
IP33
IP29 IP32
IP36
IP34
IP47
IP30 IP31
DI clock
IPP_CS
RS
WR
RD
IPP_DATA
A0
D0
PP_DATA_IN
IP28a
D1
IP28d
D2
IP27
D3
IP37 IP38
Figure 60. Asynchronous Parallel Interface Timing Diagram
Table 70. Asynchronous Display Interface Timing Parameters (Pixel Level)
ID
Parameter
Symbol
IP27 Read system cycle time
Tcycr
IP28a Address Write system cycle time Tcycwa
IP28d Data Write system cycle time
IP29 RS start
Tcycwd
Tdcsrr
IP30 CS start
Tdcsc
IP31 CS hold
Tdchc
Value
ACCESS_SIZE_#
ACCESS_SIZE_#
ACCESS_SIZE_#
UP#
UP#
DOWN#
Description
Unit
predefined value in DI REGISTER ns
predefined value in DI REGISTER ns
predefined value in DI REGISTER ns
RS strobe switch, predefined value ns
in DI REGISTER
CS strobe switch, predefined value ns
in DI REGISTER
CS strobe release, predefined
—
value in DI REGISTER
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 1
Freescale Semiconductor
93
Preliminary—Subject to Change Without Notice