68HC705JJ7_1 Datasheet, PDF (90/230 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Parallel Input/Output
When using the PB4/AN4/TCMP/CMP1 pin, the following interactions
must be noted:
1. If the OLVL timer output compare function is the required output
function, then the DDRB4 bit must be set, the PB4 data bit must
be cleared and the OPT bit in the MOR must be cleared. The
PB4/AN4/TCMP/CMP1 pin becomes an output which follows the
state of the OLVL bit. The pulldown device will be disabled in this
case. The analog subsystem would not normally use this pin as an
analog input in this case.
2. If the PB4 data bit is the required output function, then the DDRB4
bit must be set, the OLVL bit in the TCR must be cleared and the
OPT bit in the MOR must be cleared. The pulldown device will be
disabled in this case. The analog subsystem would not normally
use this pin as an analog input in this case.
3. If the comparator 1 output is the desired output function then the
PB4 data bit must be cleared, the DDRB4 bit must be set, the
OLVL bit in the TCR must be cleared and the OPT bit in the MOR
must be set. The PB4/AN4/TCMP/CMP1 pin becomes an output
which follows the state of the OLVL bit. The pulldown device will
be disabled in this case. The analog subsystem would not
normally use this pin as an analog input in this case.
4. If the PB4 pin is to be an input to the analog subsystem or a digital
input, then the DDRB4 bit must be cleared. In this case, the PB4
pin can still be read; but the voltage present will be returned as a
binary value. Depending on the external application, the PB4
pulldown may also be disabled by setting the PDIB4 pulldown
inhibit bit. In this case both the digital and analog functions
connected to this pin can be utilized.
.
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Parallel Input/Output
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