68HC705JJ7_1 Datasheet, PDF (111/230 Pages) Freescale Semiconductor, Inc – General Release Specification

Freescale Semiconductor, Inc.
Analog Subsystem
Analog Control Register
8.4 Analog Control Register
The analog control register (ACR) controls the power-up, interrupt, and
flag operation. The analog subsystem draws about 500 µA of current
while it is operating. The resulting power consumption can be reduced
by powering down the analog subsystem when not in use. This can be
done by clearing three enable bits (ISEN, CP1EN, and CP2EN) in the
ACR at $001D. Since these bits are cleared following a reset, the voltage
comparators and the charge current source will be powered down
following a reset of the device.
The control bits in the ACR are shown in Figure 8-5. All the bits in this
register are cleared by a reset of the device.
$001D Bit 7
6
5
4
3
2
1
Bit 0
Read:
CHG ATD2 ATD1 ICEN CPIE CP2EN CP1EN ISEN
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 8-5. Analog Control Register (ACR)
CHG
The CHG enable bit allows direct control of the charge current source
and the discharge device; and also reflects the state of the discharge
device. This bit is cleared by a reset of the device.
1 = If the ISEN bit is also set the charge current source is sourcing
current out of the PB0/AN0 pin. Writing a logical one enables
the charging current out of the PB0/AN0 pin.
0 = The discharge device is sinking current into the PB0/AN0 pin.
Writing a logical zero disables the charging current and
enables the discharging current into the PB0/AN0 pin, if the
ISEN bit is also set.
ATD1:2
The ATD1:2 enable bits select one of the four operating modes used
for making A/D conversions via the single-slope method.These four
modes are given in Table 8-3. These bits have no effect if the ISEN
enable bit is cleared. These bits are cleared by a reset of the device
and thereby return the analog subsystem to the manual A/D
conversion method.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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