MCIMX6U5DVM10AB Datasheet, PDF (88/168 Pages) Freescale Semiconductor, Inc – Applications Processors for Consumer Products

Electrical Characteristics
4.11.5.2 RMII Mode Timing
In RMII mode, ENET_CLK is used as the REF_CLK, which is a 50 MHz ± 50 ppm continuous reference
clock. ENET_RX_EN is used as the ENET_RX_EN in RMII. Other signals under RMII mode include
ENET_TX_EN, ENET_TX_DATA[1:0], ENET_RX_DATA[1:0] and ENET_RX_ER.
Figure 52 shows RMII mode timings. Table 63 describes the timing parameters (M16–M21) shown in the
figure.
ENET_CLK (input)
M16
M17
M18
ENET_TX_DATA (output)
ENET_TX_EN
ENET_RX_EN (input)
ENET_RX_DATA[1:0]
ENET_RX_ER
M19
M20 M21
Figure 52. RMII Mode Signal Timing Diagram
Table 63. RMII Signal Timing
ID
Characteristic
Min.
M16 ENET_CLK pulse width high
35%
M17 ENET_CLK pulse width low
35%
M18 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid
4
M19 ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid
—
M20 ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to
4
ENET_CLK setup
M21 ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold 2
Max.
Unit
65%
65%
—
15
—
ENET_CLK period
ENET_CLK period
ns
ns
ns
—
ns
4.11.5.3 Signal Switching Specifications
The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver
devices.
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3
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Freescale Semiconductor