MCIMX6U5DVM10AB Datasheet, PDF(112/168 Page) Freescale Semiconductor, Inc – Applications Processors for Consumer Products

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MCIMX6U5DVM10AB Datasheet, PDF (112/168 Pages) Freescale Semiconductor, Inc – Applications Processors for Consumer Products

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Electrical Characteristics

Table 75. Electrical and Timing Information (continued)

Symbol

FDDRCLK

PDDRCLK

tCDC

tCPH

tCPL

tSKEW[PN]

tSKEW[TX]

tSETUP[RX]

tHOLD[RX]

ïVCMTX(HF)

ïVCMTX(LF)

trlp,tflp

treo

ï¤V/ï¤tSR

ïVCMRX(HF)

ïVCMRX(LF)

CCM

eSPIKE

TMIN

VINT

fINT

Parameters

Test Conditions

Min

Typ

DDR CLK frequency

On DATAP/N outputs.

DDR CLK period

80 ïï¼= RL< = 125 ï

DDR CLK duty cycle

DDR CLK high time

tCDCï ï ï½ï tCPHï ï¯ï PDDRCLK

DDR CLK low time

DDR CLK / DATA Jitter

Intra-Pair (Pulse) skew

Data to Clock Skew

Data to Clock Receiver Setup time

Clock to Data Receiver Hold time

Differential output signal rise time

20% to 80%, RL = 50 ï

Differential output signal fall time

20% to 80%, RL = 50 ï

Common level variation above 450 MHz 80 ï<= RL< = 125 ï

Common level variation between 50

MHz and 450 MHz.

80 ï<= RL< = 125 ï

0.350

0.15

150

0.075

LP Line Drivers AC Specifications

Single ended output rise/fall time

15% to 85%, CL<70 pF

30% to 85%, CL<70 pF

Signal slew rate

15% to 85%, CL<70 pF

Load capacitance

HS Line Receiver AC Specifications

Common mode interference beyond 450

MHz

Common mode interference between 50

MHz and 450 MHz.

Common mode termination

-50

LP Line Receiver AC Specifications

Input pulse rejection

Minimum pulse response

Pk-to-Pk interference voltage

Interference frequency

450

Model Parameters used for Driver Load switching performance evaluation

Max

Unit

500

0.650

0.3UI

MHz

ps pkâpk

mVrms

mVp

120 mV/ns

200

mVpp

300

Vps

400

MHz

i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 3

112

Freescale Semiconductor

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