PCIMX515DJM8C Datasheet, PDF (85/202 Pages) Freescale Semiconductor, Inc – Processors for Consumer and Industrial Products

Electrical Characteristics
4.7.7 I²C Module Timing Parameters
This section describes the timing parameters of the I²C Module. Figure 49 depicts the timing of I²C
module, and Table 77 lists the I²C Module timing characteristics.
I2DAT
IC2
I2CLK
IC10
IC8
IC4
IC11
IC7
IC9
IC3
START
IC10
IC11
START
IC6
IC5
IC1
Figure 49. I²C Bus Timing
STOP
START
Table 77. I²C Module Timing Parameters
Standard Mode
Fast Mode
Supply Voltage =
Supply Voltage =
ID
Parameter
1.65 V–1.95 V, 2.7 V–3.3 V 2.7 V–3.3 V Unit
Min
Max
Min
Max
IC1 I2CLK cycle time
10
—
2.5
— µs
IC2 Hold time (repeated) START condition
4.0
—
0.6
— µs
IC3 Set-up time for STOP condition
IC4 Data hold time
4.0
—
0.6
— µs
0¹
3.45²
0¹
0.9² µs
IC5 HIGH Period of I2CLK Clock
4.0
—
0.6
— µs
IC6 LOW Period of the I2CLK Clock
4.7
—
1.3
— µs
IC7 Set-up time for a repeated START condition
IC8 Data set-up time
4.7
—
0.6
— µs
250
—
100³
— ns
IC9 Bus free time between a STOP and START condition
4.7
—
1.3
— µs
IC10
IC11
Rise time of both I2DAT and I2CLK signals
Fall time of both I2DAT and I2CLK signals
—
1000
20 + 0.1C_b4 300 ns
—
300
20 + 0.1C_b4 300 ns
IC12 Capacitive load for each bus line (C_b)
—
400
—
400 pF
1 _{A device must internally provide a hold time of at least 300 ns for I2DAT signal in order to bridge the undefined region of the}
falling edge of I2CLK.
2 _{The maximum hold time has only to be met if the device does not stretch the LOW period (ID no IC5) of the I2CLK signal}
3 _{A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement of Set-up time (ID No IC7)}
of 250 ns must be met. This automatically is the case if the device does not stretch the LOW period of the I2CLK signal.
If such a device does stretch the LOW period of the I2CLK signal, it must output the next data bit to the I2DAT line
max_rise_time (IC9) + data_setup_time (IC7) = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification)
before the I2CLK line is released.
4 _{Cb = total capacitance of one bus line in pF.}
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
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