PCIMX515DJM8C Datasheet, PDF (65/202 Pages) Freescale Semiconductor, Inc – Processors for Consumer and Industrial Products

Electrical Characteristics
Table 54. WEIM Asynchronous Timing Parameters Table Relative Chip Select
Ref No.
Parameter
Determination by
Synchronous measured
parameters ¹²
Max
Min
(If 133 MHz is
Unit
supported by SOC)
WE43
Input Data Valid to CSx_B MAXCO - MAXCSO + MAXDI
Invalid
MAXCO ^-
MAXCSO +
MAXDI
—
ns
WE44 CSx_B Invalid to Input Data
0
invalid
0
—
ns
WE45 CSx_B Valid to BEy_B Valid WE12 - WE6 + (WBEA - CSA)
—
(Write access)
3 + (WBEA - CSA) ns
WE46 BEy_B Invalid to CSx_B Invalid WE7 - WE13 + (WBEN - CSN)
—
(Write access)
-3 + (WBEN - CSN) ns
MAXDTI
DTACK MAXIMUM delay from
chip dtack input to its internal
FF + 2 cycles for
synchronization
—
—
—
WE47 Dtack Active to CSx_B Invalid MAXCO - MAXCSO + MAXDTI
MAXCO -
MAXCSO +
MAXDTI
—
ns
WE48 CSx_B Invalid to Dtack invalid
0
0
—
ns
1 _{Parameters WE4... WE21 value see column BCD = 0 in Table 53.}
2 _{All config. parameters (CSA,CSN,WBEA,WBEN,ADVA,ADVN,OEN,OEA,RBEA & RBEN) are in cycle units.}
3 _{CS Assertion. This bit field determines when CS signal is asserted during read/write cycles.}
4 _{CS Negation. This bit field determines when CS signal is negated during read/write cycles.}
5 _{t is axi_clk cycle time.}
6 _{BE Assertion. This bit field determines when BE signal is asserted during read cycles.}
7 _{BE Negation. This bit field determines when BE signal is negated during read cycles.}
i.MX51 Applications Processors for Consumer and Industrial Products, Rev. 6
Freescale Semiconductor
65