MC9RS08KB12 Datasheet, PDF (8/48 Pages) Freescale Semiconductor, Inc – MCU Block Diagram

Electrical Characteristics
For most applications, P_I/O << P_int and can be neglected. An approximate relationship between PD and TJ
(if P_I/O is neglected) is:
P_D = K ÷ (T_J + 273°C)
Eqn. 2
Solving Equation 1 and Equation 2 for K gives:
K = P_D × (T_A + 273°C) + θ_JA× (PD)²
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring
P_D (at equilibrium) for a known T_A. Using this value of K, the values of P_D and T_J can be obtained by
solving Equation 1 and Equation 2 iteratively for any value of T_A.
3.5 ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early
CMOS circuits, normal handling precautions must be used to avoid exposure to static discharge.
Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels
of static without suffering any permanent damage.
During the device qualification ESD stresses were performed for the human body model (HBM) and the
charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device
specification. Complete DC parametric and functional testing is performed per the applicable device
specification at room temperature followed by hot temperature, unless specified otherwise in the device
specification.
Table 5. ESD and Latch-Up Test Conditions
Model
Description
Symbol
Value
Unit
Series resistance
R1
Human
body
Storage capacitance
C
Number of pulses per pin
—
Minimum input voltage limit
—
Latch-up
Maximum input voltage limit
—
1500
Ω
100
pF
1
—
–2.5
V
7.5
V
MC9RS08KB12 Series MCU Data Sheet, Rev. 3
8
Freescale Semiconductor