33811 Datasheet, PDF (8/18 Pages) Freescale Semiconductor, Inc – Solenoid Monitor Integrated Circuit (IC)

ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 10.5V ≤ V_PWR ≤ 15.5V, - 40°C ≤ T_A ≤ 125°C, GND = 0V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T_A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI DIGITAL INTERFACE TIMING⁽¹⁰⁾
Required High State Duration on RESET for Reset to occur⁽¹¹⁾
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t _RESET
1.0
–
t _LEAD
100
–
–
µs
–
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
SI to Rising Edge of SCLK
Required Setup Time
Rising Edge of SCLK to SI
Required Hold Time
SI, CS, SCLK Signal Rise Time⁽¹²⁾
t _LAG
0
50
ns
t _{SI (SU)}
16
–
–
ns
t _{SI (HOLD)}
20
–
–
ns
t _{R (SI)}
–
5.0
–
ns
SI, CS, SCLK Signal Fall Time⁽¹²⁾
t _{F (SI)}
–
5.0
–
ns
Time from Falling Edge of CS to SO Low-impedance⁽¹³⁾
t _{SO (EN)}
–
65
80
ns
Time from Rising Edge of CS to SO High-impedance⁽¹⁴⁾
t _{SO (DIS)}
–
–
55
ns
Time from Falling Edge of SCLK to SO Data Valid⁽¹⁵⁾
t _VALID
–
65
90
ns
Sequential Transfer Rate
Time required between data transfers
t_STR
1.0
µs
Input Capacitance (SI, SCLK)
Load Capacitance (SO)
Tri-state Output Capacitance (SO)
WAVEFORM DETECTION TIMINGS
C_INPUT
C_LOAD
C_TRI-STATE
7
15
pF
200
pF
20
pF
Start of Activation Filter Time⁽¹⁶⁾
t_BEGIN
200
400
600
µs
Detection Window Time
t_WINDOW
40
53
66
ms
Sample Time
t_SAM
72
µs
Notes:
10. These parameters are guaranteed by design. Production test equipment uses 3.2MHz, 5.0V SPI interface.
11. This parameter is guaranteed by design, however it is not production tested.
12. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
13. Time required for valid output status data to be available on SO pin.
14. Time required for output states data to be terminated at SO pin.
15. Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
16. 9 µs guard band included in maximum limit
33811
8
Analog Integrated Circuit Device Data
Freescale Semiconductor