K53P144M100SF2V2 Datasheet, PDF (76/85 Pages) Freescale Semiconductor, Inc – K53 Sub-Family

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
144-pin LQFP
144-pin MAPBGA
Then use this document number
98ASS23177W
98ASA00222D
8 Pinout
8.1 K53 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
For FlexBus applications, use only the CLKOUT signal on the
PTA6 pin to ensure proper timing.
144 144 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP MAP
BGA
1 D3 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1 FB_AD27 I2C1_SDA RTC_CLKOUT
2 D2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 FB_AD26
I2C1_SCL
SPI1_SIN
3 D1 PTE2/
ADC1_SE6a ADC1_SE6a PTE2/
SPI1_SCK UART1_CTS_ SDHC0_DCLK FB_AD25
LLWU_P1
LLWU_P1
b
4 E4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN
UART1_RTS_ SDHC0_CMD FB_AD24
b
SPI1_SOUT
5 E5 VDD
VDD
VDD
6 F6 VSS
VSS
VSS
7 E3 PTE4/
DISABLED
LLWU_P2
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX SDHC0_D3 FB_CS3_b/ FB_TA_b
FB_BE7_0_b
8 E2 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2 FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
K53 Sub-Family Data Sheet, Rev. 1, 6/2012.
76
Preliminary
Freescale Semiconductor, Inc.
General Business Information