56F8322 Datasheet, PDF (76/136 Pages) Motorola, Inc – 56F8322 16-bit Hybrid Controller

5.6.20 IRQ Pending 2 Register (IRQP2)
Base + $13
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
PENDING [48:33]
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-22 IRQ Pending 2 Register (IRQP2)
5.6.20.1 IRQ Pending (PENDING)—Bits 48–33
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.21 IRQ Pending 3 Register (IRQP3)
Base + $14
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
PENDING [64:49]
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-23 IRQ Pending 3 Register (IRQP3)
5.6.21.1 IRQ Pending (PENDING)—Bits 64–49
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
5.6.22 IRQ Pending 4 Register (IRQP4)
Base + $15
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Read
PENDING [80:65]
Write
RESET
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Figure 5-24 IRQ Pending 4 Register (IRQP4)
5.6.22.1 IRQ Pending (PENDING)—Bits 80–65
This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2
through 81.
• 0 = IRQ pending for this vector number
• 1 = No IRQ pending for this vector number
56F8322 Techncial Data, Rev. 16
76
Freescale Semiconductor
Preliminary