56F8322 Datasheet, PDF (44/136 Pages) Motorola, Inc – 56F8322 16-bit Hybrid Controller

Table 4-12 Interrupt Control Registers Address Map (Continued)
(ITCN_BASE = $00 F1A0)
Register Acronym
IRQP 0
IRQP 1
IRQP 2
IRQP 3
IRQP 4
IRQP 5
ICTL
Address Offset
$11
$12
$13
$14
$15
$16
$1D
Register Description
IRQ Pending Register 0
IRQ Pending Register 1
IRQ Pending Register 2
IRQ Pending Register 3
IRQ Pending Register 4
IRQ Pending Register 5
Reserved
Interrupt Control Register
Table 4-13 Analog to Digital Converter Registers Address Map
(ADCA_BASE = $00 F200)
Register Acronym Address Offset
Register Description
ADCA_CR1
ADCA_CR2
ADCA_ZCC
ADCA_LST 1
ADCA_LST 2
ADCA_SDIS
ADCA_STAT
ADCA_LSTAT
ADCA_ZCSTAT
ADCA_RSLT 0
ADCA_RSLT 1
ADCA_RSLT 2
ADCA_RSLT 3
ADCA_RSLT 4
ADCA_RSLT 5
ADCA_RSLT 6
ADCA_RSLT 7
ADCA_LLMT 0
ADCA_LLMT 1
ADCA_LLMT 2
ADCA_LLMT 3
ADCA_LLMT 4
ADCA_LLMT 5
ADCA_LLMT 6
ADCA_LLMT 7
ADCA_HLMT 0
$0
Control Register 1
$1
Control Register 2
$2
Zero Crossing Control Register
$3
Channel List Register 1
$4
Channel List Register 2
$5
Sample Disable Register
$6
Status Register
$7
Limit Status Register
$8
Zero Crossing Status Register
$9
Result Register 0
$A
Result Register 1
$B
Result Register 2
$C
Result Register 3
$D
Result Register 4
$E
Result Register 5
$F
Result Register 6
$10
Result Register 7
$11
Low Limit Register 0
$12
Low Limit Register 1
$13
Low Limit Register 2
$14
Low Limit Register 3
$15
Low Limit Register 4
$16
Low Limit Register 5
$17
Low Limit Register 6
$18
Low Limit Register 7
$19
High Limit Register 0
56F8322 Techncial Data, Rev. 16
44
Freescale Semiconductor
Preliminary