MC13892_1107 Datasheet, PDF (74/158 Pages) Freescale Semiconductor, Inc – Power Management Integrated

FUNCTIONAL DEVICE OPERATION
SUPPLIES
Table 45. PLL Main Characteristics
Parameter
Condition ⁽⁷⁰⁾
Frequency Accuracy
Bias Current
Start up Time
PLLEN = 1
1 Buck Regulator active
2 Buck Regulators active
3 Buck Regulators active
4 Buck Regulators active
Cold Start
PFM to PWM
Notes
70. Clock input to PLL is 32.768 kHz
Min Typ Max
–
–
100
–
50
80
–
100 150
–
115
170
–
130 190
–
145 210
–
–
700
–
–
600
Units
ppm
μA
μA
μA
μA
μA
ns
ns
Table 46. PLL Control Registers
Name
R/W Reset Signal
PLLEN
R/W RESETB
PLLX[2:0] R/W RESET
Reset
State
0
100
Description
1 = Forces PLL on
0 = PLL automatically enabled
Selects PLL multiplication factor
BUCK REGULATOR CORE
Table 47. Buck Regulators (SW1, 2, 3, 4) Output Voltage Programmability
Set point
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
SWx[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
SWx Output, SWxHI = 0 (Volts)
0.600
0.625
0.650
0.675
0.700
0.725
0.750
0.775
0.800
0.825
0.850
0.875
0.900
0.925
0.950
0.975
1.000
1.025
1.050
1.075
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
SWx Output ⁽⁷¹⁾, SWxHI = 1 (Volts)
1.100
1.125
1.150
1.175
1.200
1.225
1.250
1.275
1.300
1.325
1.350
1.375
1.400
1.425
1.450
1.475
1.500
1.525
1.550
1.575
1.600
1.625
1.650
1.675
1.700
1.725
1.750
1.775
MC13892
74
Analog Integrated Circuit Device Data
Freescale Semiconductor