MC8610TPX1066JB Datasheet, PDF (72/96 Pages) Freescale Semiconductor, Inc – MPC8610 Integrated Host Processor Hardware Specifications

Hardware Design Considerations
Figure 47 provides the boundary-scan timing diagram.
JTAG
External Clock
Boundary
Data Inputs
Boundary
Data Outputs
Boundary
Data Outputs
VM
t_JTKLDX
t_JTKLDV
t_JTDVKH
VM
Input
Data Valid
t_JTDXKH
Output Data Valid
t_JTKLDZ
Output Data Valid
VM = Midpoint Voltage (OVDD/2)
Figure 47. Boundary-Scan Timing Diagram
3 Hardware Design Considerations
This section provides electrical and thermal design recommendations for successful application of the MPC8610.
3.1 System Clocking
This section describes the PLL configuration of the MPC8610. Note that the platform clock is identical to the internal MPX bus
clock.
This device includes six PLLs, as follows:
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio
between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in
Section 3.1.2, “Platform/MPX to SYSCLK PLL Ratio.”
2. The e600 core PLL generates the core clock from the platform clock. The frequency ratio between the e600 core
clock and the platform clock is selected using the e600 PLL ratio configuration bits as described in Section 3.1.3,
“e600 Core to MPX/Platform Clock PLL Ratio.”
3. The PCI PLL generates the clocking for the PCI bus
4. Each of the two SerDes blocks has a PLL.
MPC8610 Integrated Host Processor Hardware Specifications, Rev. 2
72
Freescale Semiconductor