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MC8610TPX1066JB Datasheet, PDF (1/96 Pages) Freescale Semiconductor, Inc – MPC8610 Integrated Host Processor Hardware Specifications | |||
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Freescale Semiconductor
Data Sheet
Document Number: MPC8610EC
Rev. 2, 01/2009
MPC8610 Integrated Host Processor
Hardware Specifications
Features
⢠High-performance, 32-bit e600 core, that implements the
Power Architecture⢠technology
â Eleven execution units and three register files
â Two separate 32-Kbyte instruction and data level 1 (L1)
caches
â Integrated 256-Kbyte, eight-way set-associative unified
instruction and data level 2 (L2) cache with ECC
â 36-bit real addressing
â Multiprocessing support features
â Power and thermal management
⢠MPX coherency module (MCM)
⢠Address translation and mapping units (ATMUs)
⢠DDR/DDR2 memory controller
â 64- or 32-bit data path (72-bit with ECC)
â Up to 533-MHz DDR2 data rate and up to 400 MHz
DDR data rate
â Up to 16 Gbytes memory
⢠Enhanced local bus controller (eLBC)
â Operating at up to 133 MHz
â Eight chip selects
⢠Display interface unit
â Maximum display resolution: 1280 Ã 1024
â Maximum display refresh rate: 60 Hz
â Display color depth: up to 24 bpp
â Display interface: parallel TTL
⢠OpenPIC-compliant programmable interrupt controller
(PIC)
â Supports 16 programmable interrupt and processor task
priority levels
â Supports 12 discrete external interrupts and 48 internal
interrupts
â Eight global high resolution timers/counters that can
generate interrupts
â Support for PCI Express message-shared interrupts
(MSIs)
⢠Dual I2C controllers
â Master or slave I2C mode support
â Boot sequencer
â Optionally loads configuration data from serial ROM at
reset via I2C interface
â Can be used to initialize configuration registers and/or
memory
â Supports extended I2C addressing mode
⢠DUART
⢠Fast InfraRed interface
⢠Serial peripheral interface
â Master or slave support
⢠Dual integrated four-channel DMA controllers
â All channels accessible by both local and remote masters
â Supports transfers to or from any local memory or I/O
port
â Ability to start and flow control each DMA channel
from external 3-pin interface
⢠Watchdog timer
⢠Dual global timer modules
⢠32-bit PCI interface, 33 or 66 MHz bus frequency
⢠Dual PCI Express® controllers
â PCI Express 1.0a compatible
â PCI Express controller 1 supports x1, x2, and x4 link
widths; PCI Express controller 2 supports x1, x2, x4, and
x8 link widths
â 2.5 Gbaud, 2.0 Gbps lane
⢠Device performance monitor
â Supports eight 32-bit counters that count the occurrence
of selected events
â Ability to count up to 512 counter-specific events
â Supports 64 reference events that can be counted on any
of the 8 counters
â Supports duration and quantity threshold counting
â Burstiness feature that permits counting of burst events
with a programmable time between bursts
â Triggering and chaining capability
â Ability to generate an interrupt on overflow
⢠IEEE Std 1149.1⢠compliant, JTAG boundary scan
⢠Available as 783-pin, flip-chip, plastic ball grid array
(FC-PBGA)
© Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
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