PXD10PB Datasheet, PDF (7/26 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Entry Level Display Solutions

Table 2 summarizes the operating modes of PXD10 devices.
Table 2. Operating mode summary¹
SOC features
Clock sources
Operating
modes
Wake-up time²
RUN
On OP OP On On OP OP On OP On OP — — FP — — — — — — —
HALT
CG OP OP On On OP OP On OP On OP OP OP FP — — — — — — TBD
STOP
CG CG CG On On CG CG OP OP On OP OP OP LP 50 µs 4 µs 20 µs 1ms 200 µs — 24 µs
STANDBY Off Off³ Off CG⁴ Off Off Off OP OP On OP OP OP LP 50 µs 8 µs 100 µs 1ms 200 µs Var 28 µs
Off Off Off 8K⁵ Off Off Off OP OP On OP OP OP LP 50 µs 8 µs 100 µs 1ms 200 µs Var 28 µs
POR
500 µs 8 µs 100 µs 1ms 200 µs
BAM
NOTES:
1 _{Table Key:}
On—Powered and clocked
OP—Optionally configurable to be enabled or disabled (clock gated)
CG—Clock Gated, Powered but clock stopped
Off—Powered off and clock gated
FP—VREG Full Performance mode
LP—VREG Low Power mode, reduced output capability of VREG but lower power consumption
Var—Variable duration, based on the required reconfiguration and execution clock speed
BAM—Boot Assist Module Software and Hardware used for device start-up and configuration
2 _{A high level summary of some key durations that need to be considered when recovering from low power modes. This does not account for all}
durations at wake up. Other delays will be necessary to consider including, but not limited to the external supply start-up time.
IRC Wake-up time must not be added to the overall wake-up time as it starts in parallel with the VREG.
All other wake-up times must be added to determine the total start-up time
3 _{The LCD can optionally be kept running while the device is in STANDBY mode.}
4 _{All of the RAM contents is retained, but not accessible in STANDBY mode.}
5 _{8 KB of the RAM contents is retained, but not accessible in STANDBY mode.}