PXD10PB Datasheet, PDF (20/26 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Microcontrollers for Entry Level Display Solutions

Features
2.4.21 System Timer Module (STM)
The STM is a 32-bit timer designed to support commonly required system and application software timing
functions. The STM includes a 32-bit up counter and four 32-bit compare channels with a separate
interrupt source for each channel. The counter is driven by the system clock divided by an 8-bit prescale
value (1 to 256).
• One 32-bit up counter with 8-bit prescaler
• Four 32-bit compare channels
• Independent interrupt source for each channel
• Counter can be stopped in debug mode
2.4.22 Software Watchdog Timer (SWT)
The SWT features the following:
• Watchdog supporting software activation or enabled out of reset
• Supports normal or windowed mode
• Watchdog timer value writable once after reset
• Watchdog supports optional halting during low power modes
• Configurable response on timeout: reset, interrupt, or interrupt followed by reset
• Selectable clock source for main system clock or internal 16 MHz RC oscillator clock
2.4.23 Interrupt Controller (INTC)
The INTC provides priority-based preemptive scheduling of interrupt requests, suitable for statically
scheduled hard real-time systems.
For high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral
to when the processor is executing the interrupt service routine (ISR) has been minimized. The INTC
provides a unique vector for each interrupt request source for quick determination of which ISR needs to
be executed. It also provides an ample number of priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. To allow the appropriate priorities for each source of interrupt request,
the priority of each interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority can be raised temporarily so that all tasks which share the resource can not preempt each other.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests.
These same software settable interrupt requests also can be used to break the work involved in servicing
an interrupt request into a high priority portion and a low priority portion. The high priority portion is
initiated by a peripheral interrupt request, but then the ISR asserts a software settable interrupt request to
finish the servicing in a lower priority ISR. Therefore these software settable interrupt requests can be used
instead of the peripheral ISR scheduling a task through the RTOS. The INTC provides the following
features:
PXD10 Product Brief, Rev. 1
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Freescale Semiconductor