MC9328MX21_09 Datasheet, PDF (7/100 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors

Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Signal Name
Function/Notes
RESET_IN
RESET_OUT
POR
CLKMODE[1:0]
OSC26M_TEST
TEST_WB[2:0]
TEST_WB[4:3]
WKGD
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE^® User Guide from ARM^® Limited.
TRST
TDO
TDI
TCK
TMS
JTAG_CTRL
RTCK
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is multiplexed
with 1-Wire, therefore using 1-Wire renders RTCK unusable and vice versa.
CMOS Sensor Interface
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Controller
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. LD[15:0] signals are
multiplexed with SLCDC1_DAT[15:0] from SLCDC1 and BMI_D[15:0]. LD[17] signal is multiplexed with
BMI_WRITE of BMI. LD[16] is multiplexed with BMI_READ_REQ of BMI and EXT_DMAGRANT.
FLM_VSYNC
(or simply referred
to as VSYNC)
Frame Sync or Vsync—This signal also serves as the clock signal output for gate
driver (dedicated signal SPS for Sharp panel HR-TFT). This signal is multiplexed with BMI_RXF_FULL
and BMI_WAIT of the BMI.
LP_HSYNC (or simply Line Pulse or HSync
referred to as HSYNC)
MC9328MX21 Technical Data, Rev. 3.3
Freescale Semiconductor
7