|
MC9328MX21_09 Datasheet, PDF (47/100 Pages) Freescale Semiconductor, Inc – i.MX family of microprocessors | |||
|
◁ |
Specifications
Table 31. SDRAM Read Cycle Timing Parameter (Continued)
Ref
No.
Parameter
1.8 V ± 0.1 V
Minimum Maximum
3.0 V ± 0.3 V
Minimum Maximum
Unit
4S Address setup time
3.67
â
2
â
ns
4H Address hold time
2.95
â
2
â
ns
5 SDRAM access time (CL = 3)
5 SDRAM access time (CL = 2)
5 SDRAM access time (CL = 1)
â
5.4
â
5.4
ns
â
6.0
â
6.0
ns
â
â
â
â
ns
6 Data out hold time
7 Data out high-impedance time (CL = 3)
7 Data out high-impedance time (CL = 2)
7 Data out high-impedance time (CL = 1)
8 Active to read/write command period (RC = 1)
2
â
â
â
tRCD2
â
tHZ1
tHZ1
â
â
2
â
â
â
tRCD2
â
ns
tHZ1
ns
tHZ1
ns
â
ns
â
ns
1. tHZ = SDRAM data out high-impedance time, external SDRAM memory device dependent parameter.
2. tRCD = SDRAM clock cycle time. The tRCD setting can be found in the i.MX21 reference manual.
SDCLK
CS
13
2
RAS
6
CAS
WE
ADDR
DQ
4
5
/ BA
ROW/BA
7
COL/BA
8
9
DATA
DQM
Figure 39. SDRAM Write Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.3
Freescale Semiconductor
47
|
▷ |