K51P81M100SF2V2 Datasheet, PDF (69/74 Pages) Freescale Semiconductor, Inc – K51 Sub-Family

Pinout
8 Pinout
8.1 K51 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
80 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
1 VDD
VDD
VDD
2 VSS
VSS
VSS
3 USB0_DP USB0_DP USB0_DP
4 USB0_DM USB0_DM USB0_DM
5 VOUT33
VOUT33
VOUT33
6 VREGIN
VREGIN
VREGIN
7 ADC0_DP1/ ADC0_DP1/ ADC0_DP1/
OP0_DP0 OP0_DP0 OP0_DP0
8 ADC0_DM1/ ADC0_DM1/ ADC0_DM1/
OP0_DM0 OP0_DM0 OP0_DM0
9 ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
ADC1_DP1/
OP1_DP0/
OP1_DM1
10 ADC1_DM1/ ADC1_DM1/ ADC1_DM1/
OP1_DM0 OP1_DM0 OP1_DM0
11 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
12 PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
13 PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
14 PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
15 VDDA
VDDA
VDDA
16 VREFH
VREFH
VREFH
17 VREFL
VREFL
VREFL
18 VSSA
VSSA
VSSA
19 ADC1_SE16/ ADC1_SE16/ ADC1_SE16/
OP1_OUT/ OP1_OUT/ OP1_OUT/
CMP2_IN2/ CMP2_IN2/ CMP2_IN2/
ADC0_SE22/ ADC0_SE22/ ADC0_SE22/
K51 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
69
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