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| K50P81M100SF2 Datasheet, PDF (69/72 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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81 80 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
MAP LQF
BGA P
⢠78 PTD5
/
/
PTD5
ADC0_SE6 ADC0_SE6
b
b
SPI0_PCS2 UART0_CT FTM0_CH5 FB_AD1
S_b
EWM_OUT
_b
⢠79 PTD6
/
/
PTD6
ADC0_SE7 ADC0_SE7
b
b
SPI0_PCS3 UART0_RX FTM0_CH6 FB_AD0 FTM0_FLT0
⢠â VSS
VSS
VSS
⢠80 PTD7
PTD7
CMT_IRO UART0_TX FTM0_CH7
FTM0_FLT1
Pinout
EzPort
8.2 K50 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
NOTE
The 81 MAPBGA ballmap assignments are currently being
developed.
K50 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
69
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