K40P100M72SF1 Datasheet, PDF (66/73 Pages) Freescale Semiconductor, Inc – K40 Sub-Family

Pinout
104 100 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
E5 40 VDD
VDD
VDD
G3 41 VSS
VSS
VSS
K8 42 PTA12
CMP2_IN0 CMP2_IN0 PTA12
CAN0_TX FTM1_CH0
I2S0_TXD0 FTM1_QD_
PHA
L8 43 PTA13/
LLWU_P4
CMP2_IN1 CMP2_IN1 PTA13/
LLWU_P4
CAN0_RX
FTM1_CH1
I2S0_TX_FS FTM1_QD_
PHB
K9 44 PTA14
DISABLED
PTA14
SPI0_PCS0 UART0_TX
I2S0_RX_
BCLK
I2S0_TXD1
L9 45 PTA15
DISABLED
PTA15
SPI0_SCK UART0_RX
I2S0_RXD0
J10 46 PTA16
DISABLED
PTA16
SPI0_SOUT UART0_CTS_
b/
UART0_COL_
b
I2S0_RX_FS I2S0_RXD1
H10 47 PTA17
ADC1_SE17 ADC1_SE17 PTA17
SPI0_SIN
UART0_RTS_
b
I2S0_MCLK
L10 48 VDD
VDD
VDD
K10 49 VSS
VSS
VSS
L11 50 PTA18
EXTAL0
EXTAL0
PTA18
FTM0_FLT2 FTM_CLKIN0
K11 51 PTA19
XTAL0
XTAL0
PTA19
FTM1_FLT0 FTM_CLKIN1
LPTMR0_
ALT1
J11 52 RESET_b RESET_b RESET_b
G11 53 PTB0/
LLWU_P5
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
LCD_P0/
ADC0_SE8/
ADC1_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
FTM1_CH0
FTM1_QD_ LCD_P0
PHA
G10 54 PTB1
LCD_P1/ LCD_P1/ PTB1
ADC0_SE9/ ADC0_SE9/
ADC1_SE9/ ADC1_SE9/
TSI0_CH6 TSI0_CH6
I2C0_SDA FTM1_CH1
FTM1_QD_ LCD_P1
PHB
G9 55 PTB2
LCD_P2/ LCD_P2/ PTB2
ADC0_SE12/ ADC0_SE12/
TSI0_CH7 TSI0_CH7
I2C0_SCL
UART0_RTS_
b
FTM0_FLT3 LCD_P2
G8 56 PTB3
LCD_P3/ LCD_P3/ PTB3
ADC0_SE13/ ADC0_SE13/
TSI0_CH8 TSI0_CH8
I2C0_SDA
UART0_CTS_
b/
UART0_COL_
b
FTM0_FLT0 LCD_P3
E11 57 PTB7
LCD_P7/ LCD_P7/ PTB7
ADC1_SE13 ADC1_SE13
LCD_P7
D11 58 PTB8
LCD_P8 LCD_P8 PTB8
UART3_RTS_
b
LCD_P8
E10 59 PTB9
LCD_P9 LCD_P9 PTB9
SPI1_PCS1 UART3_CTS_
b
LCD_P9
D10 60 PTB10
LCD_P10/ LCD_P10/ PTB10
ADC1_SE14 ADC1_SE14
SPI1_PCS0 UART3_RX
FTM0_FLT1 LCD_P10
C10 61 PTB11
LCD_P11/ LCD_P11/ PTB11
ADC1_SE15 ADC1_SE15
SPI1_SCK UART3_TX
FTM0_FLT2 LCD_P11
B10 62 PTB16
LCD_P12/ LCD_P12/ PTB16
TSI0_CH9 TSI0_CH9
SPI1_SOUT UART0_RX
EWM_IN LCD_P12
K40 Sub-Family Data Sheet, Rev. 2, 4/2012.
66
Freescale Semiconductor, Inc.