MFR4200 Datasheet, PDF (65/260 Pages) Freescale Semiconductor, Inc – FlexRay Communication Controllers

Memory Map and Registers
NOTE
It is not possible to mix different RS485’s in a cluster or per channel, or to
mix RS485 and Optical/Electrical PHY.
NSYNC — Node Synchronized
This read-only bit is set when the controller enters the normal state in the course of startup or reintegration.
The NSYNC is set by the CC in the NIT preceding a transition to normal operation. The NSYNC is cleared
by the CC in the NIT, prior to switching to the normal passive state (the ‘yellow’ error state; see
Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”) or the Diagnosis Stop state (the ‘red’ error
state; see Section 3.2.3.6.5, “Error Handling Level Register (EHLR)”), due to…
• …the correction value exceeding MRCR (see Section 3.2.3.3.25, “Maximum Rate Correction
Register (MRCR)”)
• …the offset correction value exceeding MOCR (see Section 3.2.3.3.24, “Maximum Offset
Correction Register (MOCR)”)
• …the CCFCR value (see Section 3.2.3.6.4, “Clock Correction Failed Counter Register (CCFCR)”)
exceeding MOCWCPR (see Section 3.2.3.5.3, “Maximum Odd Cycles Without clock Correction
Passive Register (MOCWCPR)”) or MOCWCFR (see Section 3.2.3.5.2, “Maximum Odd Cycles
Without Clock Correction Fatal Register (MOCWCFR)).
1 – Node is synchronized to cluster.
0 – Node is not synchronized to cluster.
ENSYNFF — Enable Sync Frame Filters
This bit enables/disables acceptance and rejection filtering for sync frames (see Section 3.2.3.8.1, “Sync
Frame Acceptance Filter Value Register (SYNFAFVR)”, Section 3.2.3.8.2, “Sync Frame Acceptance
Filter Mask Register (SYNFAFMR)” and Section 3.2.3.8.3, “Sync Frame Rejection Filter Register
(SYNFRFR)”).
1 – Sync frames are used for the clock synchronization only when they pass the acceptance filter and are
not rejected by the rejection filter.
0 – Sync frames are used for the clock synchronization independently of the acceptance and rejection filter.
CAE — Channel A Enable
This bit enables channel A. It can be written during the configuration state only.
1 – Channel A is enabled.
0 – Channel A is disabled.
CBE — Channel B Enable
This bit enables channel B. It can be written during the configuration state only.
1 – Channel B is enabled.
0 – Channel B disabled.
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
65