MFR4200 Datasheet, PDF (135/260 Pages) Freescale Semiconductor, Inc – FlexRay Communication Controllers

3.2.3.8.3 Sync Frame Rejection Filter Register (SYNFRFR)
Address 0xF2
Reset undefined state
15
14
13
12
11
10
Reserved
Reserved
Reserved
Reserved
Reserved SYNFRF10
r
r
r
r
r
rw
Memory Map and Registers
9
SYNFRF9
rw
8
SYNFRF8
rw
7
SYNFRF7
rw
6
SYNFRF6
rw
5
4
3
2
SYNFRF5
SYNFRF4
SYNFRF3
SYNFRF2
rw
rw
rw
rw
Figure 3-108. Sync Frame Rejection Filter Register
1
SYNFRF1
rw
0
SYNFRF0
rw
If the ENSYNFF bit is set (see Section 3.2.3.2.1, “Module Configuration Register 0 (MCR0)”), this
register is used to identify a sync frame ID whose arrival time measurement values are to be rejected for
clock synchronization. Note that this register can be written at any time by the host, unlike SYNFAFMR
and SYNFAFVR (see Section 3.2.3.8.2, “Sync Frame Acceptance Filter Mask Register (SYNFAFMR)”
and Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register (SYNFAFVR)”).
NOTE
To ensure correct operation of the CC, the host should update this register
only during the NIT.
3.2.3.8.4 Cycle Counter Filter n Register, n = [0:58] (CCFnR)
Address CCF0R=0x202, CCF1R=0x206, …, CCF57R=0x2E6, CCF58R=0x2EA.
CCFnR=0x202 + 0x4*dec2hex(n)
Reset undefined state
15
14
13
12
11
10
Reserved
Reserved
CCM5
CCM4
CCM3
CCM2
r
r
rw*
rw*
rw*
rw*
9
CCM1
rw*
8
CCM0
rw*
7
Reserved
r
6
5
4
3
2
Reserved
CCV5
CCV4
CCV3
CCV2
r
rw*
rw*
rw*
rw*
Figure 3-109. Cycle Counter Filter n Register, n = [0:58]
1
CCV1
rw*
0
CCV0
rw*
Each cycle counter filter register is related to an appropriate message buffer: CCF0R to message buffer 0,
CCF1R to message buffer 1, … , CCF58R to message buffer 58. (For more information, refer to Section ,
“Receive, receive FIFO, and transmit message buffers are accessible to the host MCU only through the
active receive, active transmit, and active receive FIFO buffers.”).
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
135