K10P64M72SF1 Datasheet, PDF (65/70 Pages) Freescale Semiconductor, Inc – K10 Sub-Family

Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64 Pin Name
LQFP
_QFN
1 PTE0
2 PTE1/
LLWU_P0
3 VDD
4 VSS
5 PTE16
6 PTE17
7 PTE18
8 PTE19
9 PGA0_DP/
ADC0_DP0/
ADC1_DP3
10 PGA0_DM/
ADC0_DM0/
ADC1_DM3
11 PGA1_DP/
ADC1_DP0/
ADC0_DP3
12 PGA1_DM/
ADC1_DM0/
ADC0_DM3
13 VDDA
14 VREFH
15 VREFL
16 VSSA
17 VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
18 DAC0_OUT/
CMP1_IN3/
ADC0_SE23
19 XTAL32
20 EXTAL32
21 VBAT
22 PTA0
23 PTA1
Default
ADC1_SE4a
ADC1_SE5a
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
XTAL32
EXTAL32
VBAT
JTAG_TCLK/
SWD_CLK/
EZP_CLK
JTAG_TDI/
EZP_DI
ALT0
ADC1_SE4a
ADC1_SE5a
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
VREFH
VREFL
VSSA
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
ADC1_SE18
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
XTAL32
EXTAL32
VBAT
TSI0_CH1
TSI0_CH2
ALT1
PTE0
PTE1/
LLWU_P0
PTE16
PTE17
PTE18
PTE19
PTA0
PTA1
ALT2
ALT3
ALT4
UART1_TX
UART1_RX
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_TX FTM_CLKIN0
UART2_RX FTM_CLKIN1
UART2_CTS_b I2C0_SDA
UART2_RTS_b I2C0_SCL
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
UART0_RX FTM0_CH6
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
FTM0_FLT3
LPTMR0_ALT3
JTAG_TCLK/ EZP_CLK
SWD_CLK
JTAG_TDI EZP_DI
K10 Sub-Family Data Sheet, Rev. 2, 4/2012.
Freescale Semiconductor, Inc.
65