K40P121M100SF2V2 Datasheet, PDF (64/70 Pages) Freescale Semiconductor, Inc – K40 Sub-Family

Pinout
8 Pinout
8.1 K40 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
E4 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1 FB_AD27 I2C1_SDA RTC_CLKOUT
E3 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 FB_AD26
I2C1_SCL SPI1_SIN
E2 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_b SDHC0_DCLK FB_AD25
F4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS_b SDHC0_CMD FB_AD24
SPI1_SOUT
E7 VDD
VDD
VDD
F7 VSS
VSS
VSS
H7 PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX
SDHC0_D3
FB_CS3_b/ FB_TA_b
FB_BE7_0_b
G4 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2 FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
F3 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS_b I2S0_MCLK FB_ALE/
FB_CS1_b/
FB_TS_b
USB_SOF_
OUT
E6 VDD
VDD
VDD
G7 VSS
VSS
VSS
L6 VSS
VSS
VSS
F1 USB0_DP USB0_DP USB0_DP
F2 USB0_DM USB0_DM USB0_DM
G1 VOUT33
VOUT33
VOUT33
G2 VREGIN
VREGIN
VREGIN
H1 ADC0_DP1 ADC0_DP1 ADC0_DP1
H2 ADC0_DM1 ADC0_DM1 ADC0_DM1
J1 ADC1_DP1 ADC1_DP1 ADC1_DP1
J2 ADC1_DM1 ADC1_DM1 ADC1_DM1
K1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DP/
ADC0_DP0/
ADC1_DP3
K40 Sub-Family Data Sheet, Rev. 1, 6/2012.
64
Preliminary
Freescale Semiconductor, Inc.
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