K10P121M100SF2V2 Datasheet, PDF (64/70 Pages) Freescale Semiconductor, Inc – K10 Sub-Family

Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
121 Pin Name
MAP
BGA
E4 PTE0
E3 PTE1/
LLWU_P0
E2 PTE2/
LLWU_P1
F4 PTE3
E7 VDD
F7 VSS
H7 PTE4/
LLWU_P2
G4 PTE5
F3 PTE6
E6 VDD
G7 VSS
F1 PTE16
F2 PTE17
G1 PTE18
G2 PTE19
L6 VSS
H1 ADC0_DP1
H2 ADC0_DM1
J1 ADC1_DP1
J2 ADC1_DM1
K1 PGA0_DP/
ADC0_DP0/
ADC1_DP3
K2 PGA0_DM/
ADC0_DM0/
ADC1_DM3
L1 PGA1_DP/
ADC1_DP0/
ADC0_DP3
L2 PGA1_DM/
ADC1_DM0/
ADC0_DM3
F5 VDDA
Default
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
DISABLED
DISABLED
DISABLED
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
VSS
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
ALT0
ADC1_SE4a
ADC1_SE5a
ADC1_SE6a
ADC1_SE7a
VDD
VSS
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
VSS
ADC0_DP1
ADC0_DM1
ADC1_DP1
ADC1_DM1
PGA0_DP/
ADC0_DP0/
ADC1_DP3
PGA0_DM/
ADC0_DM0/
ADC1_DM3
PGA1_DP/
ADC1_DP0/
ADC0_DP3
PGA1_DM/
ADC1_DM0/
ADC0_DM3
VDDA
ALT1
PTE0
PTE1/
LLWU_P0
PTE2/
LLWU_P1
PTE3
PTE4/
LLWU_P2
PTE5
PTE6
PTE16
PTE17
PTE18
PTE19
ALT2
ALT3
ALT4
SPI1_PCS1
SPI1_SOUT
UART1_TX
UART1_RX
SDHC0_D1
SDHC0_D0
SPI1_SCK UART1_CTS_b SDHC0_DCLK
SPI1_SIN UART1_RTS_b SDHC0_CMD
SPI1_PCS0 UART3_TX SDHC0_D3
SPI1_PCS2
SPI1_PCS3
UART3_RX SDHC0_D2
UART3_CTS_b I2S0_MCLK
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_TX FTM_CLKIN0
UART2_RX FTM_CLKIN1
UART2_CTS_b I2C0_SDA
UART2_RTS_b I2C0_SCL
ALT5
ALT6
ALT7
EzPort
I2C1_SDA
I2C1_SCL
RTC_CLKOUT
SPI1_SIN
SPI1_SOUT
FTM0_FLT3
LPTMR0_ALT3
K10 Sub-Family Data Sheet, Rev. 1, 6/2012.
64
Preliminary
Freescale Semiconductor, Inc.
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