DSP56364 Datasheet, PDF (64/148 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

Enhanced Serial Audio Interface Timing
Table 3-20 Enhanced Serial Audio Interface Timing (continued)
No.
Characteristics^{1, 2, 3}
Symbol
Expression
Min Max Condition⁴ Unit
443 FSR input hold time after RXC falling edge
—
—
3.0
—
x ck
ns
0.0
—
i ck a
444 Flags input setup before RXC falling edge
—
—
0.0
—
x ck
ns
19.0 —
i ck s
445 Flags input hold time after RXC falling edge
—
—
6.0
—
x ck
ns
0.0
—
i ck s
446 TXC rising edge to FST out (bl) high
—
—
— 29.0
x ck
ns
— 15.0
i ck
447 TXC rising edge to FST out (bl) low
—
448 TXC rising edge to FST out (wr) high⁶
—
449 TXC rising edge to FST out (wr) low⁶
—
—
— 31.0
x ck
ns
— 17.0
i ck
—
— 31.0
x ck
ns
— 17.0
i ck
—
— 33.0
x ck
ns
— 19.0
i ck
450 TXC rising edge to FST out (wl) high
—
—
— 30.0
x ck
ns
— 16.0
i ck
451 TXC rising edge to FST out (wl) low
—
—
— 31.0
x ck
ns
— 17.0
i ck
452 TXC rising edge to data out enable from high
—
impedance
—
— 31.0
x ck
ns
— 17.0
i ck
453 TXC rising edge to transmitter #0 drive enable —
assertion
—
— 34.0
x ck
ns
— 20.0
i ck
454 TXC rising edge to data out valid
—
455 TXC rising edge to data out high impedance⁷
—
23 + 0.5 × T_C
21.0
—
— 28.0
x ck
ns
— 21.0
i ck
— 31.0
x ck
ns
— 16.0
i ck
456 TXC rising edge to transmitter #0 drive enable —
deassertion⁷
—
— 34.0
x ck
ns
— 20.0
i ck
457 FST input (bl, wr) setup time before TXC
—
falling edge⁶
—
2.0
—
x ck
ns
21.0 —
i ck
458 FST input (wl) to data out enable from high
—
impedance
—
— 27.0
—
ns
3-48
DSP56364 Technical Data, Rev. 4.1
Freescale Semiconductor