English
Language : 

DSP56364 Datasheet, PDF (45/148 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor
External Memory Expansion Port (Port A)
Table 3-13 DRAM Out-of-Page and Refresh Timings, Four Wait States1, 2 (continued)
No.
Characteristics3
Symbol
Expression
20 MHz4
Min Max
30 MHz4
Min Max
Unit
188 WR assertion to CAS assertion
189 CAS assertion to RAS assertion
(refresh)
tWCS
3 × TC − 4.3 145.7
—
95.7
—
ns
tCSR
0.5 × TC − 4.0 21.0
—
12.7
—
ns
190 RAS deassertion to CAS assertion
(refresh)
tRPC
1.25 × TC − 4.0 58.5
—
37.7
—
ns
191 RD assertion to RAS deassertion
tROH
4.5 × TC − 4.0 221.0
—
146.0
—
ns
192 RD assertion to data valid
193 RD deassertion to data not valid3
tGA
4 × TC − 7.5
—
192.5
—
125.8 ns
tGZ
0.0
—
0.0
—
ns
194 WR assertion to data active
0.75 × TC − 0.3 37.2
—
24.7
—
ns
195 WR deassertion to data high
impedance
0.25 × TC
—
12.5
—
8.3
ns
1 The number of wait states for out of page access is specified in the DCR.
2 The refresh period is specified in the DCR.
3 RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
4 Reduced DSP clock speed allows use of DRAM out-of-page access with four Wait states (See Figure 3-17).
Table 3-14 DRAM Out-of-Page and Refresh Timings, Eight Wait States1, 2
66 MHz
80 MHz
No.
Characteristics3
Symbol Expression4
Unit
Min Max Min Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid
(read)
161 CAS deassertion to data not valid
(read hold time)
tRC
9 × TC
136.4
—
112.5
—
ns
tRAC
4.75 × TC − 7.5
—
64.5
—
—
ns
4.75 × TC − 6.5 —
—
—
52.9 ns
tCAC
2.25 × TC − 7.5
—
26.6
—
—
ns
2.25 × TC − 6.5 —
—
—
21.6 ns
tAA
3 × TC − 7.5
—
40.0
—
—
ns
3 × TC − 6.5
—
—
—
31.0 ns
tOFF
0.0
—
0.0
—
ns
162 RAS deassertion to RAS assertion
163 RAS assertion pulse width
tRP
3.25 × TC − 4.0 45.2
—
36.6
—
ns
tRAS
5.75 × TC − 4.0 83.1
—
67.9
—
ns
Freescale Semiconductor
DSP56364 Technical Data, Rev. 4.1
3-29