K40P144M100SF2V2 Datasheet, PDF (62/81 Pages) Freescale Semiconductor, Inc – K40 Sub-Family

Peripheral operating requirements and behaviors
6.8.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 44. SDHC switching specifications
Num
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
Symbol
fpp
fpp
fpp
f_OD
t_WL
t_WH
t_TLH
t_THL
t_OD
t_ISU
t_IH
Description
Min.
Max.
Operating voltage
2.7
3.6
Card input clock
Clock frequency (low speed)
Clock frequency (SD\SDIO full speed)
0
400
0
25
Clock frequency (MMC full speed)
Clock frequency (identification mode)
0
20
0
400
Clock low time
7
—
Clock high time
7
—
Clock rise time
—
3
Clock fall time
—
3
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid)
-5
6.5
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC input setup time
5
—
SDHC input hold time
0
—
Unit
V
kHz
MHz
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
Input SDHC_DAT[3:0]
SD3
SD2
SD1
SD6
SD7
SD8
Figure 24. SDHC timing
K40 Sub-Family Data Sheet, Rev. 1, 6/2012.
62
Preliminary
Freescale Semiconductor, Inc.
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