K30P100M100SF2V2 Datasheet, PDF (61/67 Pages) Freescale Semiconductor, Inc – K30 Sub-Family

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
100-pin LQFP
104-pin MAPBGA
Then use this document number
98ASS23308W
98ASA00344D
8 Pinout
8.1 K30 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
100 Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
LQFP
1 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1 FB_AD27 I2C1_SDA RTC_CLKOUT
2 PTE1/
LLWU_P0
ADC1_SE5a ADC1_SE5a PTE1/
LLWU_P0
SPI1_SOUT UART1_RX SDHC0_D0 FB_AD26
I2C1_SCL SPI1_SIN
3 PTE2/
LLWU_P1
ADC1_SE6a ADC1_SE6a PTE2/
LLWU_P1
SPI1_SCK
UART1_CTS_b SDHC0_DCLK FB_AD25
4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS_b SDHC0_CMD FB_AD24
SPI1_SOUT
5 PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_PCS0 UART3_TX
SDHC0_D3
FB_CS3_b/ FB_TA_b
FB_BE7_0_b
6 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2 FB_TBST_b/
FB_CS2_b/
FB_BE15_8_b
7 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS_b I2S0_MCLK FB_ALE/
FB_CS1_b/
FB_TS_b
8 VDD
VDD
VDD
9 VSS
VSS
VSS
10 PTE16
ADC0_SE4a ADC0_SE4a PTE16
SPI0_PCS0 UART2_TX FTM_CLKIN0
FTM0_FLT3
11 PTE17
ADC0_SE5a ADC0_SE5a PTE17
SPI0_SCK UART2_RX FTM_CLKIN1
LPTMR0_ALT3
12 PTE18
ADC0_SE6a ADC0_SE6a PTE18
SPI0_SOUT UART2_CTS_b I2C0_SDA
13 PTE19
ADC0_SE7a ADC0_SE7a PTE19
SPI0_SIN UART2_RTS_b I2C0_SCL
K30 Sub-Family Data Sheet, Rev. 1, 6/2012.
Freescale Semiconductor, Inc.
Preliminary
61
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