33993 Datasheet, PDF (6/28 Pages) Freescale Semiconductor, Inc – Multiple Switch Detection Interface

ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V ≤ V_DD ≤ 5.25 V, 8.0 V ≤ V_PWR ≤ 16 V, -40°C ≤ T_C ≤ 125°C, unless otherwise
noted. Typical values noted reflect the approximate parameter means V_PWR = 13 V, T_A = 25°C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
DIGITAL INTERFACE
Input Logic Voltage Thresholds ⁽⁹⁾
SCLK, SI, Tri-State SO Input Current
0 V to V_DD
V_INLOGIC
0.8
–
2.2
V
I_SCLK, I_SI,
µA
I_{SO (TRI)}
-10
–
10
CS Input Current
CS = V_DD
I_CS
µA
-10
–
10
CS Pull-Up Current
CS = 0 V
I_CS
µA
30
–
100
SO High-State Output Voltage
I_SO(HIGH) = -200 µA
V_{SO (HIGH)}
V
V_DD - 0.8
–
V_DD
SO Low-State Output Voltage
I_SO(HIGH) = 1.6 mA
Input Capacitance on SCLK, SI, Tri-State SO ⁽¹⁰⁾
INT Internal Pull-Up Current
V_{SO (LOW)}
–
C_IN
–
–
15
V
–
0.4
–
20
pF
40
100
µA
INT Voltage
INT = Open Circuit
INT Voltage
I _INT = 1.0 mA
V _{INT (HIGH)}
V
V_DD - 0.5
–
V_DD
V _{INT (LOW)}
V
–
0.2
0.4
WAKE Internal Pull-Up Current
WAKE Voltage
WAKE = Open Circuit
I _{WAKE (PU)}
20
40
100
µA
V _{WAKE (HIGH)}
V
4.0
4.3
5.3
WAKE Voltage
I _WAKE = 1.0 mA
V _WAKE(LOW)
V
–
0.2
0.4
WAKE Voltage
Maximum Voltage Applied to WAKE Through External Pull-Up
V _WAKE(MAX)
–
V
–
40
Notes
9. Upper and lower logic threshold voltage levels apply to SI, CS, and SCLK.
10. This parameter is guaranteed by design but is not production tested.
33993
6
Analog Integrated Circuit Device Data
Freescale Semiconductor