DSP56362 Datasheet, PDF (59/152 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

External Memory Expansion Port (Port A)
Table 3-15 DRAM Out-of-Page and Refresh Timings, Eleven Wait States^{1, 2} (continued)
100 MHz
No.
Characteristics³
Symbol Expression⁴
Unit
Min Max
182 WR assertion pulse width
t_WP
11.5 × T_C − 4.5 110.5 —
ns
183 WR assertion to RAS deassertion
t_RWL 11.75 × T_C − 4.3 113.2 —
ns
184 WR assertion to CAS deassertion
t_CWL 10.25 × T_C − 4.3 103.2 —
ns
185 Data valid to CAS assertion (write)
t_DS
5.75 × T_C − 4.0 53.5
—
ns
186 CAS assertion to data not valid (write)
t_DH
5.25 × T_C − 4.0 48.5
—
ns
187 RAS assertion to data not valid (write)
t_DHR
7.75 × T_C − 4.0 73.5
—
ns
188 WR assertion to CAS assertion
t_WCS
6.5 × T_C − 4.3 60.7
—
ns
189 CAS assertion to RAS assertion (refresh)
t_CSR
1.5 × T_C − 4.0 11.0
—
ns
190 RAS deassertion to CAS assertion (refresh)
t_RPC
2.75 × T_C − 4.0 23.5
—
ns
191 RD assertion to RAS deassertion
t_ROH
11.5 × T_C − 4.0 111.0 —
ns
192 RD assertion to data valid
193 RD deassertion to data not valid³
t_GA
10 × T_C − 7.0
93.0 ns
t_GZ
0.0
— ns
194 WR assertion to data active
0.75 × T_C − 0.3 7.2
— ns
195 WR deassertion to data high impedance
0.25 × T_C
—
2.5 ns
1 _{The number of wait states for out-of-page access is specified in the DCR.}
2 _{The refresh period is specified in the DCR.}
3 _{RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.}
4 _{The asynchronous delays specified in the expressions are valid for DSP56362.}
5 _{Either tRCH or tRRH must be satisfied for read cycles.}
Table 3-16 DRAM Out-of-Page and Refresh Timings, Fifteen Wait States 100 and 120MHz^{1, 2}
100 MHz
120 MHz
No.
Characteristics³
Symbol Expression
Unit
Min Max Min Max
157 Random read or write cycle time
158 RAS assertion to data valid (read)
159 CAS assertion to data valid (read)
160 Column address valid to data valid (read)
t_RC
t_RAC
t_CAC
t_AA
16 × T_C
160.0 — 133.3 — ns
8.25 × T_C − 5.7 —
76.8
—
63.0 ns
4.75 × T_C − 5.7 —
41.8
—
33.9 ns
5.5 × T_C − 5.7
—
49.3
40.1 ns
Freescale Semiconductor
DSP56362 Technical Data, Rev. 4
3-33