DSP56362 Datasheet, PDF (149/152 Pages) Motorola, Inc – 24-Bit Audio Digital Signal Processor

O
S
off-chip memory 3
OnCE
module timing 73
OnCE module 3, 20
Debug request 73
on-chip DRAM controller 4
On-Chip Emulation module 3
on-chip memory 3
operating mode select timing 12
P
package
144-pin TQFP 1
TQFP description 1, 3
Phase Lock Loop 6
PLL 6
Characteristics 6
performance issues 4
PLL design considerations 4, 5
PLL performance issues 5
Port A 2
Port B 2, 10, 11, 12, 13
Port C 2, 16
Port D 2, 16
power consumption design considerations 3
power management 5
program memory expansion 4
program RAM 3
R
recovery from Stop state using IRQA 12, 13
RESET 9
Reset timing 7, 10
synchronous 10
ROM, bootstrap 3
Serial Host Interface 4, 14
SHI 4, 2, 14
signal groupings 1
signals 1
functional grouping 2
SRAM 40
Access 38
read access 17
read and write accesses 14
support 4
write access 17, 18
Stop mode 5
Stop state
recovery from 12, 13
Stop timing 7
supply voltage 1
Switch mode 3
Synchronization 5
synchronous bus timings
SRAM
2 wait states 41
SRAM 1 wait state (BCR controlled) 40
synchronous interrupt from Wait state timing 12
synchronous Reset timing 10
T
TAP 3
target applications 5
Test Access Port 3
Test Access Port timing diagram 72
Test Clock (TCLK) input timing diagram 71
thermal characteristics 2
thermal design considerations 1
Timer 4, 2, 19
event input restrictions 68
interrupt generation 68
timing 68
Timing
Digital Audio Transmitter (DAX) 67
Freescale Semiconductor
DSP56362 Technical Data, Rev. 4
Index-3