56F8036 Datasheet, PDF (59/164 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Operating Modes
5.5 Operating Modes
The ITCN module design contains two major modes of operation:
• Functional Mode
The ITCN is in this mode by default.
• Wait and Stop Modes
During Wait and Stop modes, the system clocks and the 56800E core are turned off. The ITCN will signal
a pending IRQ to the System Integration Module (SIM) to restart the clocks and service the IRQ. An IRQ
can only wake up the core if the IRQ is enabled prior to entering the Wait or Stop mode.
5.6 Register Descriptions
A register address is the sum of a base address and an address offset. The base address is defined at the
system level and the address offset is defined at the module level.
Register
Acronym
IPR0
IPR1
IPR2
IPR3
IPR4
IPR5
IPR6
VBA
FIM0
FIVAL0
FIVAH0
FIM1
FIVAL1
FIVAH1
IRQP0
IRQP1
IRQP2
IRQP3
ICTRL
Table 5-3 ITCN Register Summary
(ITCN_BASE = $00 F060)
Base Address +
Register Name
$0
Interrupt Priority Register 0
$1
Interrupt Priority Register 1
$2
Interrupt Priority Register 2
$3
Interrupt Priority Register 3
$4
Interrupt Priority Register 4
$5
Interrupt Priority Register 5
$6
Interrupt Priority Register 6
$7
Vector Base Address Register
$8
Fast Interrupt Match 0 Register
$9
Fast Interrupt 0 Vector Address Low Register
$A
Fast Interrupt 0 Vector Address High 0 Register
$B
Fast Interrupt Match 1 Register
$C
Fast Interrupt 1 Vector Address Low Register
$D
Fast Interrupt 1 Vector Address High Register
$E
IRQ Pending Register 0
$F
IRQ Pending Register 1
$10
IRQ Pending Register 2
$11
IRQ Pending Register 3
Reserved
$16
Interrupt Control Register
Reserved
Section Location
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
5.6.6
5.6.7
5.6.8
5.6.9
5.6.10
5.6.11
5.6.12
5.6.13
5.6.14
5.6.15
5.6.16
5.6.17
5.6.18
5.6.19
56F8036 Data Sheet, Rev. 3
Freescale Semiconductor
59
Preliminary