K20P64M50SF0 Datasheet, PDF (57/62 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

64 64 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
MAP LQFP
BGA
E5 24 PTA2
JTAG_TDO/ TSI0_CH3 PTA2
TRACE_SWO/
EZP_DO
UART0_TX FTM0_CH7
D5 25 PTA3
JTAG_TMS/ TSI0_CH4 PTA3
SWD_DIO
UART0_RTS_ FTM0_CH0
b
G5 26 PTA4/
LLWU_P3
NMI_b/
TSI0_CH5
EZP_CS_b
PTA4/
LLWU_P3
FTM0_CH1
F5 27 PTA5
DISABLED
PTA5
USB_CLKIN FTM0_CH2
H6 28 PTA12
DISABLED
PTA12
FTM1_CH0
G6 29 PTA13/
LLWU_P4
G7 30 VDD
H7 31 VSS
H8 32 PTA18
G8 33 PTA19
DISABLED
VDD
VSS
EXTAL0
XTAL0
VDD
VSS
EXTAL0
XTAL0
PTA13/
LLWU_P4
PTA18
PTA19
FTM1_CH1
FTM0_FLT2 FTM_CLKIN0
FTM1_FLT0 FTM_CLKIN1
F8 34 RESET_b
F7 35 PTB0/
LLWU_P5
F6 36 PTB1
E7 37 PTB2
E8 38 PTB3
E6 39 PTB16
D7 40 PTB17
D6 41 PTB18
C7 42 PTB19
D8 43 PTC0
C6 44 PTC1/
LLWU_P6
B7 45 PTC2
C8 46 PTC3/
LLWU_P7
E3 47 VSS
E4 48 VDD
RESET_b
ADC0_SE8/
TSI0_CH0
ADC0_SE9/
TSI0_CH6
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
RESET_b
ADC0_SE8/
TSI0_CH0
ADC0_SE9/
TSI0_CH6
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
PTB0/
LLWU_P5
PTB1
PTB2
PTB3
TSI0_CH9 TSI0_CH9 PTB16
TSI0_CH10 TSI0_CH10 PTB17
TSI0_CH11 TSI0_CH11 PTB18
TSI0_CH12
ADC0_SE14/
TSI0_CH13
ADC0_SE15/
TSI0_CH14
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
CMP1_IN1
VSS
VDD
TSI0_CH12
ADC0_SE14/
TSI0_CH13
ADC0_SE15/
TSI0_CH14
ADC0_SE4b/
CMP1_IN0/
TSI0_CH15
CMP1_IN1
VSS
VDD
PTB19
PTC0
PTC1/
LLWU_P6
PTC2
PTC3/
LLWU_P7
I2C0_SCL FTM1_CH0
I2C0_SDA FTM1_CH1
I2C0_SCL
I2C0_SDA
SPI0_PCS4
UART0_RTS_
b
UART0_CTS_
b/
UART0_COL_
b
UART0_RX
UART0_TX
I2S0_TX_
BCLK
I2S0_TX_FS
PDB0_EXTRG
SPI0_PCS3
SPI0_PCS2
UART1_RTS_ FTM0_CH0
b
UART1_CTS_ FTM0_CH1
b
SPI0_PCS1 UART1_RX FTM0_CH2
Pinout
ALT5
ALT6
ALT7
EzPort
JTAG_TDO/ EZP_DO
TRACE_SWO
JTAG_TMS/
SWD_DIO
NMI_b
EZP_CS_b
I2S0_TX_
BCLK
I2S0_TXD0
I2S0_TX_FS
JTAG_TRST_
b
FTM1_QD_
PHA
FTM1_QD_
PHB
LPTMR0_
ALT1
FTM1_QD_
PHA
FTM1_QD_
PHB
FTM0_FLT3
FTM0_FLT0
EWM_IN
EWM_OUT_b
I2S0_TXD0
I2S0_TX_FS
I2S0_TX_
BCLK
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
57