K20P64M50SF0 Datasheet, PDF (56/62 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Pinout
8 Pinout
8.1 K20 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
64 64 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP LQFP
BGA
A1 1 PTE0
DISABLED
PTE0
UART1_TX
RTC_CLKOUT
B1 2 PTE1/
DISABLED
LLWU_P0
PTE1/
LLWU_P0
UART1_RX
C5 3 VDD
VDD
VDD
C4 4 VSS
VSS
VSS
E1 5 USB0_DP USB0_DP USB0_DP
D1 6 USB0_DM USB0_DM USB0_DM
E2 7 VOUT33 VOUT33 VOUT33
D2 8 VREGIN VREGIN VREGIN
G1 9 ADC0_DP0 ADC0_DP0 ADC0_DP0
F1 10 ADC0_DM0 ADC0_DM0 ADC0_DM0
G2 11 ADC0_DP3 ADC0_DP3 ADC0_DP3
F2 12 ADC0_DM3 ADC0_DM3 ADC0_DM3
F4 13 VDDA
VDDA
VDDA
G4 14 VREFH
VREFH
VREFH
G3 15 VREFL
VREFL
VREFL
F3 16 VSSA
VSSA
VSSA
H1 17 VREF_OUT/ VREF_OUT/ VREF_OUT/
CMP1_IN5/ CMP1_IN5/ CMP1_IN5/
CMP0_IN5 CMP0_IN5 CMP0_IN5
H2 18 CMP1_IN3/ CMP1_IN3/ CMP1_IN3/
ADC0_SE23 ADC0_SE23 ADC0_SE23
H3 19 XTAL32
XTAL32
XTAL32
H4 20 EXTAL32 EXTAL32 EXTAL32
H5 21 VBAT
VBAT
VBAT
D3 22 PTA0
JTAG_TCLK/ TSI0_CH1 PTA0
SWD_CLK/
EZP_CLK
UART0_CTS_
b/
UART0_COL_
b
FTM0_CH5
JTAG_TCLK/ EZP_CLK
SWD_CLK
D4 23 PTA1
JTAG_TDI/ TSI0_CH2 PTA1
EZP_DI
UART0_RX FTM0_CH6
JTAG_TDI EZP_DI
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
56
Freescale Semiconductor, Inc.