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K10P100M100SF2 Datasheet, PDF (57/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
100 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQF
P
1 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA
2 PTE1
ADC1_SE5a ADC1_SE5a PTE1
SPI1_SOUT UART1_RX SDHC0_D0
I2C1_SCL
3 PTE2
ADC1_SE6a ADC1_SE6a PTE2
SPI1_SCK UART1_CTS SDHC0_DCL
_b
K
4 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS SDHC0_CM
_b
D
5 PTE4
DISABLED
PTE4
SPI1_PCS0 UART3_TX SDHC0_D3
6 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
7 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS I2S0_MCLK
_b
I2S0_CLKIN
8 VDD
VDD
VDD
9 VSS
VSS
VSS
10 PTE16
ADC0_SE4a ADC0_SE4a PTE16
SPI0_PCS0 UART2_TX FTM_CLKIN
0
FTM0_FLT3
11 PTE17
ADC0_SE5a ADC0_SE5a PTE17
SPI0_SCK UART2_RX FTM_CLKIN
1
LPT00_ALT3
12 PTE18
ADC0_SE6a ADC0_SE6a PTE18
SPI0_SOUT UART2_CTS I2C0_SDA
_b
13 PTE19
ADC0_SE7a ADC0_SE7a PTE19
SPI0_SIN UART2_RTS I2C0_SCL
_b
14 ADC0_DP1 ADC0_DP1 ADC0_DP1
15 ADC0_DM1 ADC0_DM1 ADC0_DM1
16 ADC1_DP1 ADC1_DP1 ADC1_DP1
17 ADC1_DM1 ADC1_DM1 ADC1_DM1
18 PGA0_DP/ PGA0_DP/ PGA0_DP/
ADC0_DP0/ ADC0_DP0/ ADC0_DP0/
ADC1_DP3 ADC1_DP3 ADC1_DP3
19 PGA0_DM/ PGA0_DM/ PGA0_DM/
ADC0_DM0/ ADC0_DM0/ ADC0_DM0/
ADC1_DM3 ADC1_DM3 ADC1_DM3
20 PGA1_DP/ PGA1_DP/ PGA1_DP/
ADC1_DP0/ ADC1_DP0/ ADC1_DP0/
ADC0_DP3 ADC0_DP3 ADC0_DP3
21 PGA1_DM/ PGA1_DM/ PGA1_DM/
ADC1_DM0/ ADC1_DM0/ ADC1_DM0/
ADC0_DM3 ADC0_DM3 ADC0_DM3
22 VDDA
VDDA
VDDA
23 VREFH
VREFH
VREFH
24 VREFL
VREFL
VREFL
25 VSSA
VSSA
VSSA
26 VREF_OUT/ VREF_OUT VREF_OUT/
CMP1_IN5/
CMP1_IN5/
CMP0_IN5/
CMP0_IN5/
ADC1_SE18
ADC1_SE18
Pinout
EzPort
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
57