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K10P100M100SF2 Datasheet, PDF (45/63 Pages) Freescale Semiconductor, Inc – Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz | |||
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6.6.3.2
Peripheral operating requirements and behaviors
12-bit DAC operating behaviors
Table 30. 12-bit DAC operating behaviors
Symbol Description
IDDA_DACLP Supply current â low-power mode
IDDA_DACH Supply current â high-speed mode
P
tDACLP Full-scale settling time (0x080 to 0xF7F) â low-
power mode
tDACHP Full-scale settling time (0x080 to 0xF7F) â high-
power mode
tCCDACLP Code-to-code settling time (0xBF8 to 0xC08) â
low-power mode
tCCDACHP Code-to-code settling time (0xBF8 to 0xC08) â
high-speed mode
Vdacoutl DAC output voltage range low â high-speed
mode, no load, DAC set to 0x000
Vdacouth DAC output voltage range high â high-speed
mode, no load, DAC set to 0xFFF
INL Integral non-linearity error â high speed mode
DNL
DNL
Differential non-linearity error â VDACR > 2 V
Differential non-linearity error â VDACR =
VREFO (1.15 V)
VOFFSET
EG
PSRR
TCO
TGE
Offset error
Gain error
Power supply rejection ratio, VDDA > = 2.4 V
Temperature coefficient offset voltage
Temperature coefficient gain error
Min.
â
â
â
â
â
1
â
VDACR
â100
â
â
â
±0.4
±0.1
60
â
â
AC
Offset aging coefficient
â
Rop Output resistance load = 3 kΩ
â
SR
Slew rate -80hâ F7Fhâ 80h
⢠High power (SPHP)
⢠Low power (SPLP)
1.2
0.05
Typ.
â
â
100
15
â
TBD
100
â
â
â
â
â
â
TBD
TBD
â
â
1.7
0.12
Max.
150
700
200
30
5
â
TBD
VDACR
±8
±1
±1
±0.8
±0.6
90
â
â
TBD
250
â
â
Unit
μA
μA
μs
μs
μs
μs
mV
mV
LSB
LSB
LSB
%FSR
%FSR
dB
μV/C
ppm of
FSR/C
μV/yr
Ω
V/μs
Notes
1
1
1
1
2
3
4
5
5
CT
Channel to channel cross talk
BW 3dB bandwidth
⢠High power (SPHP)
⢠Low power (SPLP)
â
â
-80
dB
kHz
550
â
â
40
â
â
1. Settling within ±1 LSB
2. The INL is measured for 0+100mV to VDACRâ100 mV
3. The DNL is measured for 0+100 mV to VDACRâ100 mV
4. The DNL is measured for 0+100mV to VDACRâ100 mV with VDDA > 2.4V
K10 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
Freescale Semiconductor, Inc.
Preliminary
45
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