MSC8156E Datasheet, PDF (56/68 Pages) Freescale Semiconductor, Inc – Six-Core Digital Signal Processor with Security

Hardware Design Considerations
.
VDD Power Rail
(Voltage Regulator)
R
C1
C2
VSS
R
MSC8156E
PLL0_AVDD
PLL1_AVDD
C1
R
C2
VSS
PLL2_AVDD
C1
C2
VSS
Figure 36. PLL Supplies
Each SerDes PLL power supply must be filtered using a circuit similar to the one shown in Figure 37, to ensure stability of the
internal clock. For maximum effectiveness, the filter circuit should be placed as closely as possible to the SRn_PLL_AVDD ball
to ensure it filters out as much noise as possible. The ground connection should be near the SRn_PLL_AVDD ball. The 0.003 μF
capacitor is closest to the ball, followed by the two 2.2 μF capacitors, and finally the 1 Ω resistor to the board supply plane. The
capacitors are connected from SRn_PLL_AVDD to the ground plane. Use ceramic chip capacitors with the highest possible
self-resonant frequency. All trances should be kept short, wide, and direct.
V_DDSXC
1Ω
2.2 μF
2.2 μF
SRn_PLL_AVDD
0.003 μF
GND_SXC
Figure 37. SerDes PLL Supplies
SRn_PLL_AGND
as short as possible
3.3 Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
• Keep clock and timing signal paths as short as possible and route with 50 Ω impedance.
• Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
MSC8156E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 0
56
Freescale Semiconductor