MC1321X_09 Datasheet, PDF (55/70 Pages) Freescale Semiconductor, Inc – ZigBee™- Compliant Platform - 2.4 GHz Low Power Transceiver for the IEEE® 802.15.4 Standard plus Microcontroller

Table 15. ATD Timing/Performance Characteristics¹
Num
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
1 ATD conversion clock
f_ATDCLK 2.08V < V_DDAD < 3.6V
0.5
—
2.0
MHz
frequency
1.80V < V_DDAD < 2.08V
0.5
—
1.0
2 Conversion cycles
(continuous convert)²
CCP
28
28
<30
ATDCLK
cycles
3 Conversion time
T_conv
2.08V < V_DDAD < 3.6V
14.0
—
60.0
μS
1.80V < V_DDAD < 2.08V
28.0
—
60.0
4 Source impedance at
R_AS
input³
—
—
10
kΩ
5 Analog Input Voltage⁴
V_AIN
V_REFL
V_REFH
V
6 Ideal resolution (1 LSB)⁵
RES
2.08V < V_DDAD < 3.6V 2.031
—
3.516
mV
1.80V < V_DDAD < 2.08V 1.758
—
2.031
7 Differential non-linearity⁶
DNL
1.80V < V_DDAD < 3.6V
—
+0.5
+1.0
LSB
8 Integral non-linearity⁷
INL
1.80 V < V_DDAD < 3.6V
—
+0.5
+1.0
LSB
9 Zero-scale error⁸
E_ZS
1.80V < V_DDAD < 3.6V
—
+0.4
+1.0
LSB
10 Full-scale error⁹
E_FS
1.80V < V_DDAD < 3.6V
—
+0.4
+1.0
LSB
11 Input leakage error ¹⁰
E_IL
1.80V < V_DDAD < 3.6V
—
+0.05
+5
LSB
12 Total unadjusted
error¹¹
E_TU
1.80V < V_DDAD < 3.6V
—
+1.1
+2.5
LSB
1 _{All ACCURACY numbers are based on processor and system being in WAIT state (very little activity and no IO switching) and}
that adequate low-pass filtering is present on analog input pins (filter with 0.01 μF to 0.1 μF capacitor between analog input
and V_REFL). Failure to observe these guidelines may result in system or microcontroller noise causing accuracy errors which
will vary based on board layout and the type and magnitude of the activity.
2 _{This is the conversion time for subsequent conversions in continuous convert mode. Actual conversion time for single}
conversions or the first conversion in continuous mode is extended by one ATD clock cycle and 2 bus cycles due to starting
the conversion and setting the CCF flag. The total conversion time in Bus Cycles for a conversion is:
SC Bus Cycles = ((PRS+1)*2) * (28+1) + 2 CC Bus Cycles = ((PRS+1)*2) * (28)
3 _{RAS is the real portion of the impedance of the network driving the analog input pin. Values greater than this amount may not}
fully charge the input circuitry of the ATD resulting in accuracy error.
4 _{Analog input must be between VREFL and VREFH for valid conversion. Values greater than VREFH will convert to $3FF less the}
full scale error (E_FS).
5 _{The resolution is the ideal step size or 1LSB = (VREFH–VREFL)/1024}
6 _{Differential non-linearity is the difference between the current code width and the ideal code width (1LSB). The current code}
width is the difference in the transition voltages to and from the current code.
7 _{Integral non-linearity is the difference between the transition voltage to the current code and the adjusted ideal transition}
voltage for the current code. The adjusted ideal transition voltage is (Current Code–1/2)*(1/((V_REFH+E_FS)–(V_REFL+E_ZS))).
8 _{Zero-scale error is the difference between the transition to the first valid code and the ideal transition to that code. The Ideal}
transition voltage to a given code is (Code–1/2)*(1/(V_REFH–V_REFL)).
9 _{Full-scale error is the difference between the transition to the last valid code and the ideal transition to that code. The ideal}
transition voltage to a given code is (Code–1/2)*(1/(V_REFH–V_REFL)).
10 _{Input leakage error is error due to input leakage across the real portion of the impedance of the network driving the analog pin.}
Reducing the impedance of the network reduces this error.
MC13211/212/213 Technical Data, Rev. 1.8
Freescale Semiconductor
55