KMC7448HX1700LD Datasheet, PDF (55/60 Pages) Freescale Semiconductor, Inc – RISC Microprocessor Hardware Specifications

Document Revision History
Table 16. Valid Divide Ratio Configurations (continued)
DFS mode disabled
DFS divide-by-2 mode enabled
(HID1[DFS2] = 1 or DFS2 = 0)
DFS divide-by-4 mode enabled
(HID1[DFS4] = 1 or DFS4 = 0)
Bus-to-Core Multiplier
Configured by
PLL_CFG[0:5]
(see Table 12)
HID1[PC0-5] ³
Bus-to-Core
Multiplier
HID1[PC0-5] ³
Bus-to-Core
Multiplier
HID1[PC0-5] ³
24x
011010
12x
101110
6x
110100
28x
111010
14x
110010
7x
001000
Notes:
1. DFS mode is not supported for this combination of DFS mode and PLL_CFG[0:5] setting. As a result, the processor
will ignore these settings and remain at the previous multiplier, as reflected by the HID1[PC0-PC5] bits.
2. Though supported by the MPC7448 clock circuitry, multipliers of n.25x and n.75x cannot be expressed as valid PLL
configuration codes. As a result, the values displayed in HID1[PC0-PC5] are rounded down to the nearest valid PLL
configuration code. However, the actual bus-to-core multiplier is as stated in this table.
3. Note that in the HID1 register of the MPC7448, the PC0, PC1, PC2, PC3, PC4, and PC5 bits are bits 15, 16, 17, 18,
19, and 14 (respectively). See the MPC7450 RISC Microprocessor Reference Manual for more information.
4. Special considerations regarding snooped transactions must be observed for bus-to-core multipliers less than 5x.
See the MPC7450 RISC Microprocessor Reference Manual for more information.
9.7.5.3 Minimum Core Frequency Requirements with DFS
In many systems, enabling DFS can result in very low processor core frequencies. However, care must be
taken to ensure that the resulting processor core frequency is within the limits specified in Table 8. Proper
operation of the device is not guaranteed at core frequencies below the specified minimum f_core.
10 Document Revision History
Table 17 provides a revision history for this hardware specification.
Table 17. Document Revision History
Revision Date
Substantive Change(s)
4
3/2007 Table 19: Added 800 MHz processor frequency.
3
10/2006 Section 9.7, “Power and Thermal Management Information”: Updated contact information.
Table 18, Table 20, and Table 19: Added Revision D PVR.
Table 19: Added 600 processor frequency, additional product codes, date codes for 1400 processor
frequency, and footnotes 1 and 2.
Table 20: Added PPC product code and footnote 1.
Table 19 and Table 20: Added Revision D information for 1267 processor frequency.
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
55