K10P32M50SF0 Datasheet, PDF (53/57 Pages) Freescale Semiconductor, Inc – K10 Sub-Family

Dimensions
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ARE10566D
8 Pinout
8.1 K10 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
32 Pin Name
QFN
1 VDD
2 VSS
3 PTE16
4 PTE17
5 PTE18
6 PTE19
7 VDDA
8 VSSA
9 XTAL32
10 EXTAL32
11 VBAT
12 PTA0
13 PTA1
Default
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
VDDA
VSSA
XTAL32
EXTAL32
VBAT
JTAG_TCLK/
SWD_CLK/
EZP_CLK
JTAG_TDI/
EZP_DI
ALT0
VDD
VSS
ADC0_SE4a
ADC0_SE5a
ADC0_SE6a
ADC0_SE7a
VDDA
VSSA
XTAL32
EXTAL32
VBAT
TSI0_CH1
TSI0_CH2
ALT1
PTE16
PTE17
PTE18
PTE19
PTA0
PTA1
ALT2
ALT3
ALT4
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART2_TX FTM_CLKIN0
UART2_RX FTM_CLKIN1
UART2_CTS_b I2C0_SDA
UART2_RTS_b I2C0_SCL
UART0_CTS_ FTM0_CH5
b/
UART0_COL_b
UART0_RX FTM0_CH6
ALT5
ALT6
ALT7
EzPort
FTM0_FLT3
LPTMR0_ALT3
JTAG_TCLK/ EZP_CLK
SWD_CLK
JTAG_TDI EZP_DI
K10 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
53