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56F8355_07 Datasheet, PDF (53/164 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers
Peripheral Memory Mapped Registers
Table 4-14 Quad Timer D Registers Address Map (Continued)
(TMRD_BASE = $00 F100)
Quad Timer D is NOT available in the 56F8155 device
Register Acronym Address Offset
Register Description
TMRD0_CAP
TMRD0_LOAD
TMRD0_HOLD
TMRD0_CNTR
TMRD0_CTRL
TMRD0_SCR
TMRD0_CMPLD1
TMRD0_CMPLD2
TMRD0_COMSCR
TMRD1_CMP1
TMRD1_CMP2
TMRD1_CAP
TMRD1_LOAD
TMRD1_HOLD
TMRD1_CNTR
TMRD1_CTRL
TMRD1_SCR
TMRD1_CMPLD1
TMRD1_CMPLD2
TMRD1_COMSCR
TMRD2_CMP1
TMRD2_CMP2
TMRD2_CAP
TMRD2_LOAD
TMRD2_HOLD
TMRD2_CNTR
TMRD2_CTRL
TMRD2_SCR
TMRD2_CMPLD1
TMRD2_CMPLD2
$2
Capture Register
$3
Load Register
$4
Hold Register
$5
Counter Register
$6
Control Register
$7
Status and Control Register
$8
Comparator Load Register 1
$9
Comparator Load Register 2
$A
Comparator Status and Control Register
Reserved
$10
Compare Register 1
$11
Compare Register 2
$12
Capture Register
$13
Load Register
$14
Hold Register
$15
Counter Register
$16
Control Register
$17
Status and Control Register
$18
Comparator Load Register 1
$19
Comparator Load Register 2
$1A
Comparator Status and Control Register
Reserved
$20
Compare Register 1
$21
Compare Register 2
$22
Capture Register
$23
Load Register
$24
Hold Register
$25
Counter Register
$26
Control Register
$27
Status and Control Register
$28
Comparator Load Register 1
$29
Comparator Load Register 2
56F8355 Technical Data, Rev. 12
Freescale Semiconductor
53
Preliminary