56F8355_07 Datasheet, PDF (24/164 Pages) Freescale Semiconductor, Inc – 16-bit Digital Signal Controllers

Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal Name Pin No. Type
State
During
Reset
Signal Description
TRST
114
Schmitt
Input,
Test Reset — As an input, a low signal on this pin provides a
Input
pulled high reset signal to the JTAG TAP controller. To ensure complete
internally hardware reset, TRST should be asserted whenever RESET is
asserted. The only exception occurs in a debugging environment
when a hardware device reset is required and the JTAG/EOnCE
module must not be reset. In this case, assert RESET, but do not
assert TRST.
To deactivate the internal pull-up resistor, set the JTAG bit in the
SIM_PUDR register.
PHASEA0
(TA0)
Note: For normal operation, connect TRST directly to V_SS. If the
design is to be used in a debugging environment, TRST may be tied to
V_SS through a 1K resistor.
127
Schmitt
Input,
Phase A — Quadrature Decoder 0, PHASEA input
Input
pull-up
enabled
Schmitt
TA0 — Timer A, Channel 0
Input/
Output
(GPIOC4)
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEA0.
PHASEB0
(TA1)
To deactivate the internal pull-up resistor, clear bit 4 of the
GPIOC_PUR register.
128
Schmitt
Input,
Phase B — Quadrature Decoder 0, PHASEB input
Input
pull-up
enabled
Schmitt
TA1 — Timer A, Channel 1
Input/
Output
(GPIOC5)
Schmitt
Input/
Output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is PHASEB0.
To deactivate the internal pull-up resistor, clear bit 5 of the
GPIOC_PUR register.
56F8355 Technical Data, Rev. 12
24
Freescale Semiconductor
Preliminary