DSP56309 Datasheet, PDF (51/108 Pages) Freescale Semiconductor, Inc – 24-Bit Digital Signal Processor

AC Electrical Characteristics
Table 2-16. Host Interface Timings^1,2,12 (Continued)
No.
Characteristic¹⁰
Expression
100 MHz
Min Max
Unit
340 Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=0)^{4, 7, 8}
—
19.3 ns
341 Delay from data strobe assertion to host request deassertion for “Last Data
Register” read or write (HROD=1, open drain host request)^{4, 7, 8, 9}
—
300.0 ns
Notes:
1. See the Programmer’s Model section in the chapter on the HI08 in the DSP56309 User’s Manual.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. This timing is applicable only if two consecutive reads from one of these registers are executed.
4. The data strobe is Host Read (HRD) or Host Write (HWR) in the Dual Data Strobe mode and Host Data Strobe (HDS) in the
Single Data Strobe mode.
5. The read data strobe is HRD in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
6. The write data strobe is HWR in the Dual Data Strobe mode and HDS in the Single Data Strobe mode.
7. The host request is HREQ in the Single Host Request mode and HRRQ and HTRQ in the Double Host Request mode.
8. The “Last Data Register” is the register at address $7, which is the last location to be read or written in data transfers. This is
RXL/TXL in the Big Endian mode (HLEND = 0; HLEND is the Interface Control Register bit 7—ICR[7]), or RXH/TXH in the
Little Endian mode (HLEND = 1).
9. In this calculation, the host request signal is pulled up by a 4.7 kΩ resistor in the Open-drain mode.
10. V_CC = 3.3 V ± 0.3 V; T_J = –40°C to +100 °C, C_L = 50 pF
11. This timing is applicable only if a read from the “Last Data Register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ signal.
12. After the external host writes a new value to the ICR, the HI08 is ready for operation after three DSP clock cycles (3 × Tc).
HACK
H[0–7]
HREQ
317
327
326
318
328
329
Note: The IVR is read only by an MC680xx host processor in non-multiplexed mode.
Figure 2-27. Host Interrupt Vector Register (IVR) Read Timing Diagram
Freescale Semiconductor
DSP56309 Technical Data, Rev. 7
2-31