KMPC8315CVRAGDA Datasheet, PDF (50/106 Pages) Freescale Semiconductor, Inc – PowerQUICC II Pro Processor Hardware Specifications

PCI
Table 50. PCI AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol ¹
Min
Max
Unit
Note
Input hold from clock
t_PCIXKH
0
—
ns
2, 4
Note:
1. Note that the symbols used for timing specifications herein follow the pattern of t_{(first two letters of functional block)(signal)(state)}
(reference)(state) ^{for inputs and t}(first two letters of functional block)(reference)(state)(signal)(state) ^{for outputs. For example, t}PCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, t_SYS, reference (K) going to the high (H) state or setup time. Also, t_PCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
This table shows the PCI AC Timing Specifications at 33 MHz.
Table 51. PCI AC Timing Specifications at 33 MHz
Parameter
Symbol ¹
Min
Max
Unit
Note
Clock to output valid
t_PCKHOV
—
11
ns
2
Output hold from clock
t_PCKHOX
2
—
ns
2
Clock to output high impedance
t_PCKHOZ
—
14
ns
2, 3
Input setup to clock
t_PCIVKH
4.0
—
ns
2, 4
Input hold from clock
t_PCIXKH
0
—
ns
2, 4
Note:
1. Note that the symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)}
(reference)(state) ^{for inputs and t}(first two letters of functional block)(reference)(state)(signal)(state) ^{for outputs. For example, t}PCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, t_SYS, reference (K) going to the high (H) state or setup time. Also, t_PCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
This figure provides the AC test load for PCI.
Output
Z₀ = 50 
R_L = 50 
NVDD/2
Figure 35. PCI AC Test Load
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
50
Freescale Semiconductor