KMPC8315CVRAGDA Datasheet, PDF (48/106 Pages) Freescale Semiconductor, Inc – PowerQUICC II Pro Processor Hardware Specifications

I²C
13.2 I²C AC Electrical Specifications
This table provides the AC timing parameters for the I²C interface.
Table 48. I²C AC Electrical Specifications
All values refer to V_IH (min) and V_IL (max) levels (see Table 47)
Parameter
Symbol ¹
Min
Max Unit
SCL clock frequency
f_I2C
0
Low period of the SCL clock
t_I2CL
1.3
High period of the SCL clock
t_I2CH
0.6
Setup time for a repeated START condition
t_I2SVKH
0.6
Hold time (repeated) START condition (after this period, the first clock pulse is t_I2SXKL
0.6
generated)
400
kHz
—
s
—
s
—
s
—
s
Data setup time
t_I2DVKH
100
—
ns
Data hold time:
t_I2DXKL
s
CBUS compatible masters
—
—
I²C bus devices
0²
0.9 ³
Fall time of both SDA and SCL signals
t_I2CF ⁴
—
300
ns
Setup time for STOP condition
t_I2PVKH
0.6
—
s
Bus free time between a STOP and START condition
t_I2KHDX
1.3
—
s
Noise margin at the LOW level for each connected device (including hysteresis) V_NL 0.1  NVDD —
V
Noise margin at the HIGH level for each connected device (including hysteresis) V_NH 0.2  NVDD —
V
Note:
1. The symbols used for timing specifications follow the pattern of t_{(first two letters of functional block)(signal)(state)(reference)(state)} for
inputs and t_{(first two letters of functional block)(reference)(state)(signal)(state)} for outputs. For example, t_I2DVKH symbolizes I²C timing
(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t_I2C clock reference (K) going to
the high (H) state or setup time. Also, t_I2SXKL symbolizes I²C timing (I2) for the time that the data with respect to the start
condition (S) went invalid (X) relative to the t_I2C clock reference (K) going to the low (L) state or hold time. Also, t_I2PVKH
symbolizes I²C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative
to the t_I2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used
with the appropriate letter: R (rise) or F (fall).
2. MPC8315E provides a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge
the undefined region of the falling edge of SCL.
3. The maximum t_I2DVKH has to be met only if the device does not stretch the LOW period (t_I2CL) of the SCL signal.
4. MPC8315E does not follow the I2C-BUS Specifications version 2.1 regarding the tI2CF AC parameter.
This figure provides the AC test load for the I²C.
Output
Z₀ = 50 
R_L = 50 
NVDD/2
Figure 33. I²C AC Test Load
MPC8315E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
48
Freescale Semiconductor