IMX35_1 Datasheet, PDF (50/148 Pages) Freescale Semiconductor, Inc – i.MX35 Applications Processors for Industrial and Consumer Products

NOTE
The clock will continue to run unless both CKEs are low. Then the clock
will be stopped in low state.
Table 35. SDRAM Self-Refresh Cycle Timing Parameters
ID
SD16
Parameter
CKE output delay time
Symbol
tCKS
Min.
1.8
Max.
—
Unit
ns
SDCLK
SDCLK
CS
DDR4
RAS
CAS
DDR4
WE
DDR4
DDR5
DDR4
DDR5
DDR1
DDR2
DDR3
DDR5
DDR5
CKE
DDR6
ADDR
ROW/BA
DDR7
COL/BA
DDR4
Figure 31. DDR2 SDRAM Basic Timing Parameters
Table 36. DDR2 SDRAM Timing Parameter Table
ID
PARAMETER
DDR1 SDRAM clock high-level width
DDR2 SDRAM clock low-level width
DDR3 SDRAM clock cycle time
DDR4 CS, RAS, CAS, CKE, WE setup time
Symbol
tCH
tCL
tCK
tIS¹
DDR2-400
Min
Max
0.45
0.55
0.45
0.55
7.0
8.0
0.35
—
Unit
tCK
tCK
ns
ns
i.MX35 Applications Processors for Industrial and Consumer Products, Rev. 6
50
Freescale Semiconductor