PXN20PB Datasheet, PDF (5/23 Pages) Freescale Semiconductor, Inc – 32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking

2.3 PXN21 Block Diagram
Figure 2 shows a top-level block diagram of the PXN21.
PXN21 Block Diagram
Debug
JTAG
Nexus3 (Z6)
Nexus2+ (Z0)
e200z0 Core
VLE
Masters
e200z650 Core
VLE
MMU (32 TLB)
FPU/SPE
32 KB Cache
4/8 Way
32 kHz
XTAL
128 kHz
IRC
4–40 MHz
XTAL
FMPLL
Semaphores
32-ch DMA
Mux
16 MHz
IRC
Crossbar Switch (XBAR)
Memory Protection Unit (MPU)
Features
VREG
Controller
RTC/API
SWT
STM
INTC
PIT
BAM
SIU
2 MB
Flash
(ECC)
ECSM
PBRIDGE B
8 x UART/LIN
2 x I²C
64 x ADC
2 x SPI
32 x eMIOS
5 x CAN
CTU
PBRIDGE A
4 x UART/LIN
2 x SPI
2 x I²C
128 KB
SRAM
(ECC)
Standby RAM
ECSM
ADC
BAM
CAN
CTU
ECC
ECSM
eDMA
eMIOS
FMPLL
I²C
INTC
JTAG
– Analog-to-digital converter
– Boot assist module
– Controller area network controller
– Cross triggering unit
– Error correction code
– Error correction status module
– Enhanced direct memory access controller
– Timed input/output
– Frequency-modulated phase-locked loop
– Inter-integrated circuit controller
– Interrupt controller
– Joint Test Action Group interface
MPU
– Memory protection unit
NDI
– Nexus debug interface
PBRIDGE – Peripheral I/O bridge
PIT
– Periodic interrupt timer
RTC
– Real time clock
SIU
– System integration unit
SPI
– Serial peripheral interface controller
STM
– System timer module
SWT
– Software watchdog timer
UART/LIN – Universal asynchronous receiver/transmitter/
local interconnect network
VREG – Voltage regulator
Figure 2. PXN21 Block Diagram
2.4 Critical Performance Parameters
The critical performance parameters of the PXN20 devices feature the following:
• Fully static design operation up to a maximum of 116 MHz, based on 105 C ambient
PXN20 Product Brief, Rev. 1
Freescale Semiconductor
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